Powertech Technology Inc.

Chi-Chung Yu

Hung-Hsin Hsu

Shih-Chun Chen

Ying-Lin Chen

Sheng-I Huang

Ta-Hao Chang

I-Fong Wu

A method for manufacturing a chip package structure having a coating layer is provided. At least one chip package structure is mounted onto a terminal-protection film. The chip package structure has a top side, a back side opposite to the top side and a plurality of lateral sides. A plurality of terminals is disposed on the back side. The terminal-protection film at least partially seals the back side. A coating layer is formed over the top side, the lateral sides and a periphery region of the chip package structure, wherein the coating layer is not formed on the back side and the terminals. The terminal-protection film is debonded from the chip package structure.

Method for manufacturing a chip package having a coating layer

A universal substrate includes a plurality of inner pads and a plurality of outer pads. A plurality of bifurcate wirings and a plurality of fuses are formed on a surface of the substrate. The fuses are connected with the bifurcate wirings in series. By the bifurcate wirings and the fuses, each of the inner pads is electrically connected to all of the outer pads to provide optional electrical disconnections therebetween. Accordingly, the universal substrate can provide for various chips with different serial arrangements of bonding pads without replacing or manufacturing another kind of substrate.

Universal substrate for a semiconductor device having selectively activated fuses

Growing community of inventors

Hsinchu County, Taiwan

Chi-Chung Yu