Siliconware Precision Industries Co., Ltd.

Chi-Chuan Wu

Randy H Y Lo

Chien-Ping Huang

Han-Ping Pu

Jui-Yu Chuang

Tzong-Dar Her

Lien-Chi Chan

Tzong-Da Ho

Ming-Chih Hsieh

Eric Ko

Ke-Chuan Yang

Chih-Shun Chen

Randy Hy Lo

Po-Hao Yuan

Cheng-Shiu Hsiao

Lien-Chih Chan

Jui-Yi Chuang

Chieh-Yuan Lin

Ssu-Cheng Lai

Jui Yu Chuang

A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.

Method for fabricating flip-chip semiconductor package with lead frame as chip carrier

Flip-chip semiconductor package with lead frame as chip carrier and fabrication method thereof

A flip-chip semiconductor package with a lead frame and a method for fabricating the same are provided. The lead frame has a plurality of leads, each lead having an upper surface, a lower surface, and an inner end directed toward the center of the lead frame. A recessed portion is formed on the upper surface of the inner end of each lead, making the inner end shaped as a stepped structure. The depth of the recessed portion is equal to a height of a reflow-collapsed solder bump that is for electrically connecting a chip to the lead. At least one chip is electrically connected to the leads in a flip-chip manner via a plurality of solder bumps bonded to the recessed portions. An encapsulation body is formed to encapsulate the lead frame, chip and solder bumps, with the lower surfaces of the leads being exposed from the encapsulation body.

Flip-chip semiconductor package with lead frame and method for fabricating the same

A method is proposed for fabricating a TFBGA (Thin & Fine Ball-Grid Array) package with embedded heat spreader. Conventionally, since an individual TFBGA package is quite small in size, it would be highly difficult to incorporate an embedded heat spreader therein. As a solution to this problem, the proposed method utilizes a single substrate predefined with a plurality of package sites, and further utilizes a heat-spreader frame including an integrally-formed matrix of heat spreaders each corresponding to one of the package sites on the substrate. A batch of semiconductor chips are then mounted on the respective package sites on the substrate. During the encapsulation process, a single continuous encapsulation body is formed to encapsulate the entire heat-spreader frame and all the semiconductor chips. After ball implantation, a singulation process is performed to cut apart the encapsulation body into individual package units, each serving as the intended TFBGA package. In the foregoing process, since the entirety of the heat-spreader frame is relatively large in size as compared to the size of an individual TFBGA package, it can be easily handled, so that the embedding of a heat spreader in each package unit can be easily carried out.

Method of fabricating a thin and fine ball-grid array package with embedded heat spreader

A method is proposed for fabricating a TFBGA (Thin & Fine Ball-Grid Array) package with embedded heat spreader. Conventionally, since an individual TFBGA package is quite small in size, it would be highly difficult to incorporate an embedded heat spreader therein. As a solution to this problem, the proposed method utilizes a single substrate predefined with a plurality of package sites, and further utilizes a heat-spreader frame including an integrally-formed matrix of heat spreaders each corresponding to one of the package sites on the substrate. A batch of semiconductor chips are then mounted on the respective package sites on the substrate. During the encapsulation process, a single continuous encapsulation body is formed to encapsulate the entire heat-spreader frame and all the semi-conductor chips. After ball implantation, a singulation process is performed to cut apart the encapsulation body into individual package units, each serving as the intended TFBGA package. In the foregoing process, since the entirety of the heat-spreader frame is relatively large in size as compared to the size of an individual TFBGA package, it can be easily handled, so that the embedding of a heat spreader in each package unit can be easily carried out.

A heat sink with a collapse structure and a semiconductor device with the heat sink are proposed, in which the heat sink is in ladder-like shape due to a height difference formed between an extending portion and an body of the heat sink, and the body has at least one surface exposed to outside of the semiconductor package. The extending portion produces collapse deformation in response to stress from engagement of molds in a molding process, so as to prevent a semiconductor chip from being damaged by the stress. The heat sink directly attached to the chip allows heat generated by the chip to pass through the extending portion to the body of the heat sink, and then the heat can be dissipated through the exposed surface of the body to the outside of the semiconductor package, so as to improve the heat dissipating efficiency.

Heat sink with collapse structure for semiconductor package

A method of packaging a multi chip module (MCM) with low cost and high reliability is disclosed. In the MCM process, a plurality of bare chips and CPSs, such as CPU or memory device, are integrated on a substrate to increase the package density. The method discards the high cost KGD process and directly takes the thin and small CSPs passing the tests as KGD and integrates the chips and CSPs into ball grid array package (BGA package) so that the cost is reduced and the yield and quality of the package is improved.

Method of packaging multi chip module

A QFN semiconductor package and a fabrication method thereof are proposed, wherein a lead frame having a plurality of leads is adopted, and each lead is formed at its inner end with a protruding portion. A wire bonding region and a bump attach region are respectively defined on opposite surfaces of the protruding portion, and staggered in position. This allows a force applied from a wire bonder to the wire bonding regions not to adversely affect solder bumps implanted on the bump attach regions, so that the solder bumps can be structurally assured without cracking. Moreover, the wire bonding regions spaced apart from the bump attach regions can be prevented from being contaminated by an etching solution used in solder bump implantation, so that wire bonding quality can be well maintained.

Semiconductor package and fabricating method thereof

A super low profile package with stacked dies comprises a substrate, a heat spreader, a first die, a second die, a molding compound, and a number of solder balls. The substrate has a cavity, a top surface and a bottom surface opposite to the top surface. The heat spreader is connected to the bottom surface of the substrate, and a portion of the heat spreader opposite to the cavity serves as a die pad. The first die seated in the cavity is attached to the die pad while the second die seated in the cavity is attached to the first die, and both dies are wire-bonded to the substrate for electrical connection. The molding compound fills the cavity and encapsulates the first die, the second die, the heat spreader, and part of the bottom surface of the substrate. Numerous solder balls are attached to the bottom surface of the substrate. The benefits resulting from the package of the invention include a reduction of profile, a simple manufacturing process, and a low prime cost.

Super low profile package with stacked dies

An improved tape carrier package (TCP) structure is proposed, which is characterized in the provision of dummy pads and dummy leads to help reinforce the package construction. The dummy pads are provided on the corners of the semiconductor chip, while the dummy leads are bonded between the dummy pads and corner-situated lead-bonding areas on the tape carrier. During assembly, since dummy leads are bonded between the dummy pads and corner-situated lead-bonding areas, the corners of the semiconductor chip can be firmly supported as well as the four sides of the semiconductor chip which are supported by the I/O leads. As a result the package construction is reinforced. During inner-lead bonding (ILB) process, such reinforcement can help prevent the cracking of the I/O leads. Moreover, during encapsulation process, the provision of the dummy leads can help allow the encapsulation material to be more evenly distributed to the back side of the semiconductor chip, thus preventing undesired forming of voids in the resulted encapsulation body, making the resulted encapsulation body less likely subjected to popcorn effect and delamination. In addition, it can help provide a uniform package height (UPH) to the overall package construction. These advantages allow the finished TCP product to be more assured in quality and reliability.

Tape carrier package structure with dummy pads and dummy leads for package reinforcement

A method is proposed for mounting a passive component, such as a resistor or a capacitor, over an IC package substrate, such as a BGA (Ball Grid Array) substrate. Conventionally, the mounting of a passive component over a substrate would result in the undesired existence of a gap between the passive component and the substrate, which could lead to such problems as bridged short-circuit, popcorn effect, and dismounting of the passive component during subsequent processes. As a solution to these problems, the proposed method utilizes an electrically-insulative material, such as epoxy resin, to fill up the gap between the passive component and the substrate. Various techniques can be employed to fill the electrically-insulative material into the gap, including dispensing and stencil printing. Due to the fact that the proposed method allows no gap to be left between the passive component and the substrate, it can help eliminate the drawbacks of the prior art, thus allowing the manufactured IC package to be more assured in quality and more reliable to use.

Method of mounting a passive component over an integrated circuit package substrate

A lead frame and a flip chip semiconductor package having the lead frame are proposed, in which a die pad of the lead frame is elevated with a height difference relative to leads of the lead frame, and the height difference cannot exceed the vertical height of a plurality of solder bumps, which electrically connect a semiconductor chip to the lead frame. In a reflow process, due to good wetability of the lead frame, the solder bumps keep collapsing, allowing the semiconductor chip placed above the die pad to gradually move downwardly until abutting the die pad, which then stops the chip from moving, so as to force the solder bumps to stop collapsing to be maintained with a certain height. This therefore helps eliminate the occurrence of over-collapsing of the solder bumps, and thus assure bonding quality between the solder bumps and the lead frame.

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Taichung, Taiwan

Chi-Chuan Wu