Delta Electronics, Inc.

Chi-Cheng Lin

Hsin-Chang Tsai

Chia-Yen Lee

A wafer-level chip scale package is disclosed, including a chip including a substrate and a GaN transistor disposed on the substrate. The GaN transistor includes a first electrode, a dielectric layer disposed on the chip, and a redistribution trace disposed on the first dielectric layer and electrically connected with the first electrode, wherein the redistribution trace has a linear side and a curved side on opposite sides along its longitudinal direction.

Growing community of inventors

Taoyuan Hsien, Taiwan

Chi-Cheng Lin