Taiwan Semiconductor Manufacturing Comp. Ltd.

Winbond Electronics Corporation

Lyontek Inc.

Cheertek Incorporation

Chi-Cheng Hung

Yu-Sheng Wang

Wei-Liang Lin

Ching-Hwanq Su

Chun-Kuang Chen

Ru-Gun Liu

Chia-Ching Lee

Shiu-Ko JangJian

Jun-Nan Nian

Kei-Wei Chen

Liang-Yueh Ou Yang

Tsai-Sheng Gau

Yung-Sung Yen

Chung-Chiang Wu

De-Fang Chen

Yu-Tien Shen

Kuan-Ting Liu

Ming-Ching Chung

Yi-Wei Chiu

Ming-Hsing Tsai

Kuei-Shun Chen

Chen-Yuan Kao

Yueh-Ching Pai

Chin-Yuan Tseng

Chia-Yang Wu

Horng-Huei Tseng

Chin-Hsiang Lin

Ying-Lang Wang

Yu-Ting Lin

Kuan-Hsin Lo

Ching-Yu Chang

Chih-Ming Lai

Yen-Ming Chen

Huan-Just Lin

Chi-Cherng Jeng

Da-Yuan Lee

Hsin-Yi Lee

Chih-Yuan Ting

Chien-Wei Wang

Ya Hui Chang

Jung-Chih Tsao

Hung-Hsu Chen

Wen-Hsi Lee

Yu-Ren Peng

Yuan-Hsiang Lung

Jyun-Ru Wu

Ming-Huei Weng

Ting-Siang Su

Ling-Yueh Chang

Weng-Cheng Chen

Hao-Han Wei

Li-Jui Chen

Chi-Wen Liu

Ziwei Fang

Shih-Chieh Chang

Fu-Kai Yang

Chun-Hsiung Lin

Ken-Hsien Hsieh

Wen-Chun Huang

Tzung-Chi Fu

Yuan-Ching Peng

Jyh-Cherng Sheu

Sheng-Hsiung Wang

Rong-Fuh Shyu

Chun-I Tsai

Fu-Jye Liang

Chih-Chung Chang

Jian-Shin Tsai

Meng-Wei Chen

Chih-Chang Huang

Jhih-Yu Wang

Ta-Ching Yu

Ing-Ju Lee

Hsien-Huang Liao

Pohan Kung

Wen Hao Liu

Jack Chang

Chien-Yu Li

Wen-I Chu

Ying-Jing Lu

Ming-Sen Tung

Iu-Ren Chen

Pwu-Yueh Chung

Pei-Shan Chang

Pei-Wen Wu

A semiconductor device includes a source/drain region, a silicide region, a source/drain contact, and a silicon-containing dielectric liner. The source/drain region is in a substrate. The silicide region is embedded in the source/drain region. The source/drain contact is over the silicide region. The silicon-containing dielectric liner surrounds the source/drain contact. The source/drain region is in contact with an outer sidewall of the silicon-containing dielectric liner but separated from a bottom surface of the silicon-containing dielectric liner by the silicide region.

Semiconductor device with dielectric spacer liner on source/drain contact

A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

FinFET structures and methods of forming the same

A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Methods for forming contact plugs with reduced corrosion

In some implementations, one or more semiconductor processing tools may deposit cobalt material within a cavity of the semiconductor device. The one or more semiconductor processing tools may polish an upper surface of the cobalt material. The one or more semiconductor processing tools may perform a hydrogen soak on the semiconductor device. The one or more semiconductor processing tools may deposit tungsten material onto the upper surface of the cobalt material.

Tungsten deposition on a cobalt surface

A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.

Metal adhesion layer to promote metal plug adhesion

Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.

Method for improved critical dimension uniformity in a semiconductor device fabrication process

A semiconductor device includes a semiconductor substrate, a gate structure, a first source/drain region, a second source/drain region, first source/drain contact and a first dielectric spacer liner. The gate structure is over the semiconductor substrate. The first source/drain region and the second source/drain region are in the semiconductor substrate and respectively on opposite sides of the gate structure. The first source/drain contact is over the first source/drain region. The first dielectric spacer liner lines a sidewall of the first source/drain contact and extends into the first source/drain region.

A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.

Semiconductor device and methods of manufacture

A method of manufacturing a semiconductor device includes: providing a substrate; forming a gate structure on the substrate; depositing a first dielectric layer over the gate structure; depositing a conductive interconnect in a trench of the first dielectric layer thereby exposing a surface of the conductive interconnect through the first dielectric layer; depositing a conductive layer over the exposed surface of the conductive interconnect; depositing a silicon-containing layer over the conductive layer and the conductive interconnect; and forming a metal silicide layer to be a silicide form of the conductive layer by reacting the conductive layer with silicon in the silicon-containing layer.

Semiconductor device and manufacturing process thereof

A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.

Pattern fidelity enhancement with directional patterning technology

A method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer. The method further includes removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A portion of the metal layer has a crystalline structure. The method further includes filling a remaining portion of the recess with metallic materials, wherein the metallic materials are overlying the metal layer.

N-work function metal with crystal structure

A method of fabricating tantalum nitride barrier layer in an ultra low threshold voltage semiconductor device is provided. The method includes forming a high-k dielectric layer over a semiconductor substrate. Subsequently, a tantalum nitride barrier layer is formed on the high-k dielectric layer. The tantalum nitride barrier layer has a Ta:N ratio between 1.2 and 3. Next, a plurality of first metal gates is formed on the tantalum nitride barrier layer. The first metal gates are patterned, and then a second metal gate is formed on the tantalum nitride barrier layer.

Method of fabricating tantalum nitride barrier layer and semiconductor device thereof

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Tainan, Taiwan

Chi-Cheng Hung