United Microelectronics Corp.

Chewnpu Jou

David Lee

Roger Yen

A method of fabricating a MOS capacitor in a complementary MOS fabrication process with dual-doped poly gates comprises providing a substrate of a first conductive type, the substrate having a first well of the first conductive type and a second well of a second conductive type. A dielectric layer is formed on the substrate. A first poly gate of the first conductive type is formed on the dielectric layer over the first well and a second poly gate of the second conductive type is formed on the dielectric layer over the second well. A first doped region of the first conductive type is formed in the substrate at each side of the first poly gate. A second doped region of the second conductive type is formed in the substrate at each side of the second poly gate layer. A spacer is formed on sidewalls of the first poly gate and the second poly gate, wherein a portion of the dielectric layer is also removed to expose a portion of the first doped region and a portion of the second doped region. An implantation is performed on the exposed portion of the first doped region with dopants of the first conductive type, so as to form a first substrate electrode. An implantation process is performed on the exposed portion of the second doped region with dopants of the second conductive type to form a second substrate electrode.

Method of fabricating a MOS capacitor

The present invention provides an integrated inductor device having a high Q value, a low stray capacitance, and a small area that are compatible with conventional RF CMOS process. The inductor device has a plurality of conductive paths collocated in the same space for each gate, drain, and source of a RF transistor. The conductive paths are formed as a square-loop with 90 degrees turns with a space between adjacent conductive paths. Wherein the conductive paths are formed inside while staying geometrically parallel to each other. The adjacent conductive path carries a current in the same direction so all the conductive paths give positive contribution to a total magnetic flux.

Integrated inductor for RF transistor

A method of fabricating an interconnect of a capacitor. A substrate having a capacitor is provided. The capacitor comprises a bottom electrode electrically connected to the substrate, a dielectric layer and a top electrode thereon. A spin-on dielectric layer is formed on the substrate and the capacitor. The spin-on dielectric layer on the substrate is thicker than that on the top electrode. The spin-on dielectric layer is etched back until the top electrode is exposed. A patterned metal layer is formed on the spin-on dielectric layer and the top electrode with a bottom surface in directly contact with a top surface of the top electrode.

Method of fabricating interconnect of capacitor

A method for manufacturing an inductor. A silicon substrate of a first conductive type is provided. A spiral conductive layer is formed over the silicon substrate. A doped region of a second conductive type is formed in the substrate below the spiral conductive layer. A doped region of the first conductive type is next formed in the substrate around the doped region of the second conductive type. A reverse-bias voltage is applied to the doped region of the first conductive type and the doped region of the second conductive type. The application of a reverse-bias voltage creates a depletion region beneath the doped region of the second conductive type and the space between the doped regions.

Method of manufacturing an inductor

An inductor. A silicon substrate of a first conductive type is provided. A spiral conductive layer is formed over the silicon substrate. A doped region of a second conductive type is formed in the substrate below the spiral conductive layer. A doped region of the first conductive type is next formed in the substrate around the doped region of the second conductive type. A reverse-bias voltage is applied to the doped region of the first conductive type and the doped region of the second conductive type. The application of a reverse-bias voltage creates a depletion region beneath the doped region of the second conductive type and the space between the doped regions.

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Hsinchu Hsien, Taiwan

Chewnpu Jou