Chartered Semiconductor Manufacturing Ltd (corporation)

Chew-Hoe Ang

Jia-Zhen Zheng

Elgin Kiok Quek

Mei-Sheng Zhou

Daniel Yen

Eng-Hua Lim

Jia Zhen Zheng

Randall Cha

Wenhe Lin

Eng Hua Lim

Cher-Liang Cha

Mei Sheng Zhou

Elgin Kiok Boone Quek

Randall Cher Liang Cha

Tupei Chen

Shyue-Seng Tan

Jeffrey Chee Wei-Lun

Daniel Lee-Wei Yen

This invention provides a circuit and a method for generating a low-level current using semiconductor charge pumping. The invention provides a means of generating a range of current sources by varying the frequency of a repetitive voltage pulse input signal. Also, this invention utilizes one or many MOSFET devices in order to produce higher levels of current. The current source embodiments of this invention generate very stable current sources with high input impedances.

Charge pump current source

A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width &ldquo;L&rdquo;. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width &ldquo;1&rdquo;. The re-flowed first opening lower width &ldquo;1&rdquo; being less than the pre-reflowed first opening width &ldquo;L&rdquo;. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width &ldquo;1&rdquo;. Removing the patterned, re-flowed masking layer. A small feature material is then formed within the second opening and any excess small feature material above the etched spacing layer is removed. The etched spacing layer is removed to form the small feature comprised of the small feature material.

Method to pattern small features by using a re-flowable hard mask

A method for forming a dual Si&mdash;Ge poly-gates having different Ge concentrations is described. An NMOS active area and a PMOS active area are provided on a semiconductor substrate separated by an isolation region. A gate oxide layer is grown overlying the semiconductor substrate in each of the active areas. A polycrystalline silicon-germanium (Si&mdash;Ge) layer is deposited overlying the gate oxide layer wherein the polycrystalline Si&mdash;Ge layer has a first Ge concentration. The NMOS active area is blocked while the PMOS active area is exposed. Successive cycles of Ge plasma doping and laser annealing into the PMOS active area are performed to achieve a second Ge concentration higher than the first Ge concentration. The polycrystalline Si&mdash;Ge layer is patterned to form a gate in each of the active areas wherein the gate in the PMOS active area has a higher Ge concentration than the gate in the NMOS active area to complete formation of dual Si&mdash;Ge polysilicon gates with different Ge concentrations in the fabrication of an integrated circuit device.

Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization

A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the composite insulator stack. Selective removal of specific components of the composite insulator stack, in a specific region, allows the depth of the channel openings to be varied. A subsequent epitaxial silicon growth procedure fills the variable depth channel openings, providing the variable length, channel regions for the vertical CMOS devices.

Method of fabricating variable length vertical transistors

A method of structures having dual gate oxide thicknesses, comprising the following steps. A substrate having first and second pillars is provided. The first and second pillars each having an outer side wall and an inner side wall. At least one of the outer or inner side walls of at least one of the first and second pillars is/are masked leaving at least one of the outer or inner side walls of at least one of the first and second pillars exposed. Dopants are then implanted through the at least one of the exposed outer or inner side walls modifying the surface of the at least one of the doped exposed outer or inner side walls. The at least one of the masked outer or inner side walls of at least one of the first and second pillars is/are unmasked. Gate oxide is grown on the outer side walls and the inner side walls of the first and second pillars wherein the gate oxide grown upon the modified surfaces of the at least one of the doped outer or inner side walls is thicker than the gate oxide grown upon the non-modified surfaces of the at least one of the non-doped outer or inner side walls.

Forming dual gate oxide thickness on vertical transistors by ion implantation

A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si N or an SiO /Si N stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.

Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask

A method of fabricating dual gate oxide thicknesses comprising the following steps. A substrate is provided having a first pillar and a second pillar. A gate dielectric layer is formed over the substrate and the first and second pillars. First and second thin spacers are formed over the gate dielectric layer covered side walls of the first and second pillars respectively. The second pillar is masked leaving the first pillar unmasked. The first thin spacers are removed from the unmasked first pillar. The mask is removed from the masked second pillar. The structure is oxidized to convert the second thin spacers to second preliminary gate oxide over the previously masked second pillar and to form first preliminary gate oxide over the unmasked first pillar. The second gate oxide over the second pillar being thicker than the first gate oxide over the first pillar. The thinner first preliminary gate oxide is removed from over the first pillar and the thicker second preliminary gate oxide is thinned from over the second pillar. First final gate oxide is formed over the first pillar and second final gate oxide is formed on the second pillar. The second final gate oxide including the thinned second preliminary gate oxide. The second final gate oxide over the second pillar being thicker than the first final gate oxide over the first pillar.

Method of fabricating CMOS device with dual gate electrode

A method of fabricating a dual gate electrode CMOS device having dual gate electrodes. An N&plus; poly gate is used for the nMOSFET and a metal gate is used for the pMOSFET. The N&plus; nMOSFET poly gate may be capped with a highly conductive metal to reduce its gate resistance. A sacrificial cap is used for the N&plus; poly gate to eliminate a mask level for the dual gate electrodes.

A new method is provided for the creation of layers of gate oxide of different thicknesses. A substrate is provided, the surface of the substrate is divided into a first surface region over which a thick layer of gate oxide has to be created and a second surface region over which a thin layer of gate oxide is to be created. Thick gate-oxide implants are performed into the surface of the substrate. A thick layer of gate oxide is created over the surface of the substrate, the thick layer of gate oxide is successively patterned for thin gate-oxide implants, comprising thin gate-oxide n-well/p-well, threshold, punchthrough implants, into the second surface region of the substrate. The thick layer of gate oxide is removed from the second surface region of the substrate. The (now contaminated) top layer of the thick layer of gate oxide is removed, a thin layer of gate oxide is grown over the second surface region of the substrate.

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Singapore, Singapore

Chew-Hoe Ang