Jcet Group Co., Ltd.

Chenye He

Yaojian Lin

Shuo Liu

Danfeng Yang

Chen Xu

The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes an interposer, chips, and warpage adjustment structures, wherein the interposer includes a first surface and a second surface opposite thereto, and the chips are electrically connected to the first surface of the interposer; the warpage adjustment structures are symmetrically distributed with respect to a center of the first surface; and each of the warpage adjustment structures include a warpage adjustment piece and/or a cavity filled with a plastic packaging material, the warpage adjustment piece is disposed on the first surface, and the cavity is located outside conducting structures and sinks inward along the first surface. By cooperation between the warpage adjustment pieces and the cavities filled with the plastic packaging material, the warpage of the interposer in horizontal and vertical directions can be reduced.

Packaging structure and manufacturing method thereof

The present invention provides an antenna packaging structure and a manufacturing method thereof. An antenna and a chip are respectively disposed on two sides of a substrate layer, antenna layers are formed by an antenna support member, a first antenna layer located above the antenna support member and a second antenna layer located below the antenna support member together, and interlayer dielectrics of the antenna support member and the antenna layers are low dielectric loss materials, so that a heterogeneous and isomerous antenna structure is formed, thereby reducing the problems such as current leakage and stray capacitance in the packaging structure caused by dielectric loss, and reducing a size of the antenna packaging structure.

Antenna packaging structure and manufacturing method thereof

The present invention provides a package structure and a method for manufacturing the same. The package structure includes at least two electrical elements, a second reconstruction layer, and a metal lead frame, wherein at least one of the electrical elements is a chip, at least one of the electrical elements has a first reconstruction layer, and the second reconstruction layer has a smaller pin pitch than that of the metal lead frame; the second reconstruction layer has a first surface and a second surface, a functional surface of the electrical element is disposed on and connected to the first surface, and at least one of the electrical elements is connected to the second reconstruction layer; and the second surface is disposed on and connected to the metal lead frame. A fan-out package structure is formed on the metal lead frame, which improves the heat dissipation capacity of the chip.

Growing community of inventors

Wuxi, China

Chenye He