Zhuzhou Crrc Times Electric Co., Ltd

Chinese Academy of Sciences

Chengzhan Li

Guoyou Liu

Xinyu Liu

Yun Bai

Yidan Tang

Chengyue Yang

Yudong Wu

Yunbin Gao

Jingjing Shi

Yanli Zhao

Huajun Shen

Jingtao Zhou

The present disclosure discloses a self-aligned silicon carbide MOSFET device with an optimized Pregion and a manufacturing method thereof. The self-aligned silicon carbide MOSFET device is formed by a plurality of silicon carbide MOSFET device cells connected in parallel, and these silicon carbide MOSFET device cells are arranged evenly. The silicon carbide MOSFET device cell comprises two source electrodes, one gate electrode, one gate oxide layer, two Nsource regions, two Pcontact regions, two P wells, one Ndrift layer, one buffer layer, one Nsubstrate, one drain electrode and one isolation dielectric layer. By optimizing the Pregion, the present disclosure forms a good source ohmic contact, reduces the on-resistance, and also shorts the source electrode and the P well to prevent the parasitic transistor effect of the parasitic NPN and PiN, which may take both conduction characteristics and the breakdown characteristics of the device into consideration, and may be applied to a high voltage, high frequency silicon carbide MOSFET device. The self-aligned manufacturing method used in the present disclosure simplifies the process, controls a size of a channel accurately, and may produce a lateral and vertical power MOSFET.

Silicon carbide MOSFET device and method for manufacturing the same

A silicon carbide MOSFET device is disclosed. The silicon carbide MOSFET device includes a gate oxide layer which is constituted by a first gate oxide layer and a second gate oxide layer. A thickness of the second gate oxide layer is larger than a thickness of the first gate oxide layer. Through dividing the gate oxide layer into two parts with different thicknesses, i.e., enabling the gate oxide layer to have a staircase shape, an electric field strength of the gate oxide layer can be effectively reduced, while a threshold voltage and a gate control property of the device are not affected. An on-resistance of the device can be reduced through increasing a width of a JFET region. A method for manufacturing the silicon carbide MOSFET device is further disclosed.

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Zhuzhou, China

Chengzhan Li