International Business Machines Corporation

Cheng-Yih Liu

Vincent L Rideout

Donald A Soderman

Ronald P Esch

Robert M Folsom

James Economy

Ernest Bassous

Mary Ann Flandera

G Thomas Wenning

George T Wenning

A method for forming via holes having a rounded sidewall profile includes exposing a layer or organic positive photoresist to a formic gas plasma while the surface of the photoresist layer is bombarded with ions and electrons in a high voltage biased environment in which the photoresist layer is capacitively coupled. The photoresist layer may be exposed to UV light either before or after the formic gas plasma step.

Fabrication method for controlled via hole process

Continuous films are formed on a substrate by coating said substrate with a solution of a diacetylenic prepolymer in a liquid phenylacetylene solvent and reacting the solvent with the prepolymer.

Preparation of continuous films of diacetylenic polymers

A dynamic random access memory is fabricated on a monolithic chip of semiconductor material. The memory is formed of an array of memory cells controlled for reading and writing by word and bit lines which are selectively connected to the cells. Each cell is a single field effect transistor structure having improved electrical charge storage capability. The improved charge storage capability of each cell is provided by an electrical capacitance structure uniquely arranged and formed as an integral portion of the field effect transistor structure. The gate electrode of each field effect transistor structure is connected to a predetermined one of said word lines. The drain of each field effect transistor is connected to a predetermined one of said bit lines. The source of each field effect transistor structure is integrally connected to and forms a portion of the uniquely arranged electrical capacitance structure of the field effect transistor structure. The electrical capacitance or storage node structure of each cell has increased electrical charge storage capacity and may be considered as a single capacitor. The single (storage) capacitor of each cell is provided between the source of the field effect transistor, a source of reference potential (reference plane) and the monolithic semiconductor substrate on which the memory is fabricated. The arrangement of the memory cells, the structure and material of each of the memory cells, and a method of fabricating the entire memory is disclosed. Also disclosed is an improved field effect transistor structure and process for fabricating same. The process of fabrication, cell arrangement and the improved storage node of each memory cell, as structurally fabricated and uniquely arranged, provides a monolithic memory having improved density and operating characteristics.

Method of fabricating random access memory device

One-device monolithic random access memory and method of fabricating same

A silicon etchant is disclosed composed of an aqueous solution of a fluoride ion and oxygen maintained at a substantially neutral pH. The etchant eliminates the problems of stripping organic photoresists, maintaining silicon/phosphosilicate glass selectively, silicon surface pitting, oxide residues, and insoluble reaction products.

Neutral pH silicon etchant for etching silicon in the presence of

A family of etchants for polycrystalline silicon based upon an aqueous solution of NR.sub.4 OH, where R is an alkyl group, has a relatively low etching rate enabling the exercise of better control over the delineation of fine structures.

Growing community of inventors

Woodbridge, VA, United States of America

Cheng-Yih Liu