Taiwan Semiconductor Manufacturing Comp. Ltd.

Cheng-Yeh Shih

Chue-San Yoo

Yu-Hua Lee

Kuo Ching Huang

Mong-Song Liang

Jenn Ming Huang

Yean-Kuen Fang

Dun Nian Yaung

Shau-Lin Shue

Jin-Yuan Lee

Shou-Gwo Wuu

Chung-Long Chang

Cheng-Ming Wu

Wen-Chuan Chiang

Yuan-Chang Huang

Chwen-Ming Liu

Min-Hsiung Chiang

Tse-Liang Ying

James Cheng-Ming Wu

Kuei-Ying Lee

James (Cheng-Ming) Wu

Chie-Ming Yang

Kan-Yuan Lee

Jun-Yang Lai

Hui-Chi Lin

Yi-Lin Sun

Jiann-Liang Liou

Wing-Lang Zang

Shu-Hui Chen

Wen-Chan Lin

A process for creating a storage node electrode, for a DRAM cell, exhibiting increased surface area resulting from the formation of an agglomerated metal silicide layer, on the top surface of the storage node electrode, has been developed. The process features creating a polysilicon, storage node electrode shape, followed by the formation of an overlying, agglomerated titanium disilicide layer. The agglomerated titanium disilicide layer is formed from a RTA procedure, applied to a smooth titanium disilicide layer, located on the polysilicon, storage node electrode.

Capacitor with a roughened silicide layer

A method and structure for forming a modified field oxide region having increased field oxide threshold voltages (V ) and/or reduced leakage currents between adjacent device areas is achieved. The method involves forming a field oxide using the conventional local oxidation of silicon (LOCOS) using a patterned silicon nitride layer as a barrier to oxidation. After forming the LOCOS field oxide by thermal oxidation and removing the silicon nitride, a conformal insulating layer composed of silicon oxide is deposited and anisotropically etched back to form sidewall insulating portions over the bird's beak on the edge of the LOCOS field oxide, thereby forming a new modified field oxide. P-channel implants are formed in the device areas. Then a second implant is used to implant through the modified field oxide to provide channel-stop regions with modified profiles that increase the field oxide V and/or reduce leakage current between device areas. This improved field oxide/channel-stop structure is particularly useful for reducing the leakage current on DRAM cells thereby increasing the refresh cycle times.

Method of making an improved field oxide isolation structure for semiconductor integrated circuits having higher field oxide threshold voltages

A new method is provided for treating the surface of a layer of passivation where this layer of passivation comprises silicon dioxide or silicon nitride. An oxygen rich layer is created over the surface of the layer of passivation. Under the first embodiment of the invention a layer of silicon oxide is deposited over the surface of a substrate, a layer of plasma enhanced silicon nitride is deposited over the surface of the layer of silicon oxide, and a layer of oxynitride is deposited over the surface of the layer of plasma enhanced silicon nitride. Under the second embodiment of the invention a layer of silicon oxide is deposited over the surface of a substrate, a layer of silicon nitride is deposited over the surface of layer of silicon oxide. The surface of the layer of silicon nitride is oxidized by N O or O plasma treatment.

Method to improve adhesion of molding compound by providing an oxygen rich film over the top surface of a passivation layer

A method of forming self aligned contacts in silicon integrated circuit wafers which has a reduced contact resistance is described. A contact hole formed in a layer of dielectric is filled with polysilicon using a split polysilicon process. A first polysilicon layer is deposited after the contact hole is opened. The first polysilicon is preferably, but not necessarily, high temperature film doped polysilicon. The first polysilicon is then treated using C F /O . A second polysilicon layer, preferably furnace doped polysilicon, is then deposited to completely fill the contact hole. The wafer is then planarized, using chemical mechanical polishing or back etching, leaving polysilicon completely filling the contact hole and forming a low resistance contact.

Self aligned contact plug technology

A method is disclosed for forming self-aligned, borderless contact and vias together and simultaneously with relaxed photolithographic alignment tolerances using a modified dual damascene process having two etch-stop layers. A first etch-stop layer is formed over a first dielectric layer. A second dielectric layer and a second etch-stop layer are next formed sequentially over the first etch-stop layer. Contact/via hole pattern is etched into the first etch-stop layer using a first photoresist layer. A second photoresist layer, patterned with metal line trench pattern, is formed over the contact/via patterned first etch-stop layer. The contact/via hole openings are etched into the first dielectric layer until the second etch-stop layer is reached. Then, both the first and second etch-stop layers are etched through the openings. The openings in the first and second etch-stop layers are both extended by etching the second and first dielectric layers, respectively, until the former opening reaches the second etch-stop layer, and the latter reaches the underlying substructure of devices within the semiconductor substrate. Thus, a combination of contact via interconnects, without borders, and self-aligned with respect to metal lines with relaxed photolithographic tolerances is formed together and simultaneously using a modified dual damascene process having two etch-stop layers.

Borderless dual damascene contact

An improved method to form self-aligned contacts with polysilicon plugs is described. A semiconductor substrate is provided. A silicon oxide layer overlying the semiconductor substrate is deposited. A contact hole is etched through the silicon oxide layer to the surface of the semiconductor substrate. A polysilicon layer is deposited overlying the silicon oxide layer and filling completely the contact hole. The polysilicon layer is polished away to define only polysilicon remaining in the contact hole and to remove the silicon oxide layer sufficient to flatten the top surface of the silicon oxide layer. The fabrication of the integrated circuit device is completed.

Method to form self-aligned contacts with polysilicon plugs

This invention provides a method for forming a self aligned contact plug with low contact resistance in a semiconductor device using a two step process of (1) forming a high temperature polysilicon film and (2) forming a furnace doped polysilicon layer. The process begins by providing a substrate structure, having a first gate structure and a second gate structure thereon and having a contact area between the first gate structure and the second gate structure. An inter level dielectric layer is formed over the first gate structure and the second gate structure. The interlevel dielectric layer is patterned to form a self aligned contact opening over the contact area. Impurity ions are implanted into the substrate structure through the self aligned contact opening to form source and drain regions. In the key steps, a high temperature polysilicon film is formed over the source and drain regions, and a furnace doped polysilicon layer is formed over the high temperature polysilicon film. The furnace doped polysilicon layer and the high temperature polysilicon film are planarized to form a polysilicon self aligned contact plug.

Method for fabricating a self aligned contact plug

A method of fabricating a metal guard ring (e.g., 139 149 159) around for a metal fuse 141 and fuse opening 88. The metal fuse 41 is formed from a second metal layer (M2) (or M3 or M4, etc.) and is connected to an underlying polysilicon layer 22 by fuse interconnections 129A 129B. The method comprises:

Fabrication of metal fuse design for redundancy technology having a

A method for forming protection layers completely around a metal fuse to protect the metal fuse 74A and metal lines 74B from moisture corrosion from fuse opening and micro-cracks in dielectric layers. The invention surrounds the fuse on all sides with two protection layers: a bottom protection layer 70 and a top protection layer 78. The top protection layer 78 is formed over the fuse metal, the sidewalls of the metal fuse and the bottom protection layer 70. The protection layers 70 78 of the invention form a moisture proof seal structure around the metal fuse 74A and protect the metal fuse 74A and metal lines 74B from moisture and contaminates.

Method to form a protected metal fuse

A process for creating an insulator filled, shallow trench, in a semiconductor substrate, in which the insulator layer in the shallow trench, is not exposed to procedures used to remove defining composite insulator layers, has been developed. The process features creating a lateral recess, in a thick silicon nitride layer, used as a component of a composite insulator layer, where the composite insulator layer is used for subsequent definition of the shallow trench, in the semiconductor substrate. An insulator deposition, filling openings, and recesses, in the composite insulator layer, and filling the shallow trench, followed by removal of excess insulator fill, on the top surface of the composite insulator layer, results in the formation of a 'T' shape insulator, comprised of an insulator shape, in the shallow trench, and comprised of a wider insulator shape, located in the composite insulator shape, with the lateral recess in the thick silicon nitride layer, and with the wider insulator shape, overlying the narrow, insulator shape, in the shallow trench. The insulator, in the shallow trench, is protected from the procedure used to remove components of the composite insulator layer, by the wider insulator shape.

Shallow trench isolation technology to eliminate a kink effect

A contact between a conductor and a substrate region in a MOSFET SRAM device is formed by a dielectric layer on the surface of a partially completed SRAM device with pass transistors and latch transistors with the dielectric layer being formed above those pass and latch transistors. A thin film transistor gate electrode and an interconnection line are formed on the upper surface of the dielectric layer. A gate oxide layer covers the gate electrode and the interconnection line. A polysilicon conductive layer which covers the gate oxide layer includes a channel region between a source region and a drain region which are formed on opposite sides of the channel region. There is a channel mask formed self-aligned with the channel region formed above the channel region as well as being above the gate electrode. The polysilicon conductive layer is doped aside from the channel mask thereby providing a source region and a drain region on opposite sides of the channel region. A doped interconnect line is also formed in the polysilicon conductive layer. There is a contact which extends through the gate oxide layer between the interconnection line and the polysilicon conductive layer.

SRAM memory device with improved performance

A method and structure for forming a modified field oxide region having increased field oxide threshold voltages (V.sub.th) and/or reduced leakage currents between adjacent device areas is achieved. The method involves forming a field oxide using the conventional local oxidation of silicon (LOCOS) using a patterned silicon nitride layer as a barrier to oxidation. After forming the LOCOS field oxide by thermal oxidation and removing the silicon nitride, a conformal insulating layer composed of silicon oxide is deposited and anisotropically etched back to form sidewall insulating portions over the bird's beak on the edge of the LOCOS field oxide, thereby forming a new modified field oxide. P-channel implants are formed in the device areas. Then a second implant is used to implant through the modified field oxide to provide channel-stop regions with modified profiles that increase the field oxide V.sub.th and/or reduce leakage current between device areas. This improved field oxide/channel-stop structure is particularly useful for reducing the leakage current on DRAM cells thereby increasing the refresh cycle times.

Method of making an improved field oxide isolation structure for

A method for making cylinder-shaped stacked capacitors for DRAMs is described. A planar first insulating layer is formed over device areas. An etch-stop layer, a second insulating layer, and a polish-back endpoint detect layer are deposited in which cylinder-shaped capacitors with node contacts are formed. First openings for node contacts are etched in the polish-back and second insulating layers to the etch-stop layer aligned over the device areas. Wider second openings, aligned over the first openings, are etched through the polish-back layer, and also removes the etch-stop layer in the first openings. The second insulating layer in the second openings is etched to the etch-stop layer, while the first insulating layer is etched in the first openings for node contact openings. A doped first polysilicon layer is deposited and polished back to the polish-back detect layer to form concurrently the node contacts in the first openings and bottom electrodes in the second openings. The second insulating layer is removed by a wet etch. A thin dielectric layer is deposited, and top electrodes are formed from a second polysilicon layer. The etch-stop layer provides better control of the etching depth for the first and second openings that improves reliability while providing a simple manufacturing process.

Method for making cylinder-shaped capacitors for dynamic random access

A method of forming a contact between a conductor and a substrate region in a MOSFET SRAM starts with forming a dielectric layer on the surface of a partially completed SRAM device with pass and latch transistors covering the transistors. Then, form a thin film gate electrode and an interconnect on the dielectric layer with a gate oxide layer covering the gate electrode and the interconnect; cover the gate oxide layer with a poly conductive layer. Then form a silicon oxide layer over the poly conductive layer and pattern the silicon oxide layer to form a silicon oxide channel mask over the poly conductive layer which is used to pattern the silicon oxide layer into a channel mask over the gate electrode. The channel mask is used for patterning the implanting of dopant into the poly conductive layer aside from the channel mask to form a source region, a drain region and an interconnect in the poly conductive layer. Then form a contact through the gate oxide layer between the interconnect and the poly conductive layer by forming a tungsten layer over the poly conductive layer aside from the channel mask which remains in place.

Method for manufacturing a TFT SRAM memory device with improved

A method for making improved capacitor bottom electrodes (capacitor nodes) having longer refresh cycle times and increased capacitance for DRAM cells has been achieved. The method involves using a polysilicon high-temperature film (HTF) instead of the conventional doped polysilicon to form the node capacitors. After forming the DRAM pass transistors (FETs) and depositing an insulating layer, node contact openings are etched in the insulator to the drain of the FET. The capacitor bottom electrodes are formed by depositing a polysilicon HTF at a temperature of at least 650.degree. C. using a reactant gas mixture of H.sub.2 /SiH.sub.4 /PH.sub.3, which results in a longer refresh cycle time and increased capacitance. This results in a significantly improved final die yield. After forming an interelectrode dielectric layer on the bottom electrodes, another doped polysilicon layer is deposited to form the top electrodes to complete the DRAM cells.

Growing community of inventors

Hsin-Chu, Taiwan

Cheng-Yeh Shih