Taiwan Semiconductor Manufacturing Comp. Ltd.

Cheng-Wei Lian

Chih-Wei Lin

Kang-Min Kuo

Chih-Lin Wang

Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure over a substrate and forming a sealing layer surrounding the dummy gate structure. The method includes forming a spacer covering the sealing layer and removing the dummy gate structure to form a trench. The method further includes forming an interfacial layer and a gate dielectric layer. The method further includes forming a capping layer over the gate dielectric layer and partially oxidizing the capping layer to form a capping oxide layer. The method further includes forming a work function metal layer over the capping oxide layer and forming a gate electrode layer over the work function metal layer. In addition, a bottom surface of the capping oxide layer is higher than a bottom surface of the spacer.

Method for manufacturing gate structure with additional oxide layer

Semiconductor structures and method for forming the same are provided. The method for manufacturing the semiconductor structure includes forming a first gate dielectric layer over a substrate and forming a first capping layer over the first gate dielectric layer. The method for manufacturing the semiconductor structure includes oxidizing the first capping layer to form a first capping oxide layer and forming a first work function metal layer over the first capping oxide layer. The method for manufacturing the semiconductor structure includes forming a first gate electrode layer over the first work function metal layer.

Gate structure with additional oxide layer and method for manufacturing the same

Methods for forming a semiconductor structure are provided. The method includes forming a first dummy gate structure and forming first spacers over a sidewall of the first dummy gate structure. The method includes removing the first dummy gate structure to form a first trench between the first spacers and forming a first capping layer in the first trench. A first portion of the first capping layer covers a sidewall of the first trench and a second portion of the first capping layer covers a bottom surface of the first trench. The method further includes oxidizing a sidewall of the first portion of the first capping layer and a top surface of the second portion of the first capping layer to form a first capping oxide layer and forming a first work function metal layer and forming a first gate electrode layer over the first work function metal layer.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The gate structure includes a gate dielectric layer formed over the substrate and a capping layer formed over the gate dielectric layer. The gate structure further includes a capping oxide layer formed over the capping layer and a work function metal layer formed over the capping oxide layer. The gate structure further includes a gate electrode layer formed over the work function metal layer.

Gate structure with additional oxide layer

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the substrate, and an insertion layer formed over the interfacial layer. The semiconductor structure further includes a gate dielectric layer formed over the insertion layer and a gate structure formed over the gate dielectric layer. The insertion layer and the gate dielectric layer may be metal oxides where the insertion layer has an oxygen coordination number greater than the gate dielectric layer.

Semiconductor structure with insertion layer and method for manufacturing the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the substrate, and an insertion layer formed over the interfacial layer. The semiconductor structure further includes a gate dielectric layer formed over the insertion layer and a gate structure formed over the gate dielectric layer. In addition, the insertion layer is made of MO, and Mis a metal, O is oxygen, and x is a value greater than 4.

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New Taipei, Taiwan

Cheng-Wei Lian