Taiwan Semiconductor Manufacturing Comp. Ltd.

Wistron Corporation

Au Optronics Corporation

Wistron Neweb Corporation

Tsinghua University

Cheng-Wei Chang

Yi-Ying Liu

Sung-Li Wang

Chia-Hung Chu

Min-Hsiu Hung

Shuen-Shin Liang

Shahaji B More

Yu-Ting Lin

Hsu-Kai Chang

Ken-Yu Chang

Chien-Shun Liao

Kao-Feng Lin

Huang-Yi Huang

Yueh-Ching Pai

Yu Shih Wang

Chun Chieh Wang

Yi-Wei Chiu

Fang-Wei Lee

Hung-Yi Huang

Chun-I Tsai

Yi-Hsiang Chao

Yu-Ming Huang

Wan Hsuan Hsu

Yean-Zhaw Chen

I-Hsiu Wang

Hsin-Yan Lu

Ethan Tseng

Hua-Chen Fan

Shu-Lan Chang

Keng-Chu Lin

Ming-Hsi Yeh

Chun-Chieh Wang

Chen-Yi Liang

Chih-Chien Chi

Chen-Yuan Kao

Chun-Neng Lin

Wei-Chen Chen

Hsueh-Shih Chen

Chien-Hua Chen

Chia-Tien Li

Chen Yi Liang

Fang-Wen Liao

Che-Wen Liu

Po-Nan Yeh

U-Ting Chiu

Ci-Guang Peng

Chi-Yu Chou

Shen-Pin Wei

Kuan-Kan Hu

Wei-Shan Chang

Te-Hen Lo

Chang-Wei Yeh

Yi-Feng Wu

Chuan-Hui Shen

Chun-Lung Hsiao

Keng-Hsien Yang

Hsin Ting Ho

Hong-Ming Wu

Shu-Ting Jhuang

Chih-Teng Shen

Li-Hsiang Chao

Kai-Cheng Wang

Hung Pin Lu

Ching-Che Hung

Yu-Hao Luo

Chi-Hsiang Huang

Kai-Ting Huang

Guan-Hong Chen

Chun-Chi Huang

Ping-Chang Yang

Cheng Hung Chen

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first side and a second side opposing the first side, a source/drain epitaxial feature disposed adjacent the first side of the substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, and a third epitaxial layer having sidewalls surrounded by and in contact with the second epitaxial layer. The device structure also includes a first silicide layer in contact with the substrate, the first, second, and third epitaxial layers, a first source/drain contact extending through the substrate from the first side to the second side, and a first metal capping layer disposed between the first silicide layer and the first source/drain contact.

Semiconductor device with backside power rail and methods of fabrication thereof

A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.

Method of forming conductive feature including cleaning step

Some implementations described herein provide a nanostructure transistor including inner spacers between a gate structure and a source/drain region. The inner spacers, formed in cavities at end regions of sacrificial nanosheets during fabrication of the nanostructure transistor, include concave-regions that face the source/drain region. Formation techniques include forming the sacrificial nanosheets and inner spacers to include certain geometric and/or dimensional properties, such that a likelihood of defects and/or voids within the inner spacers and/or the gate structure are reduced.

Semiconductor device and methods of formation

In an embodiment, a device includes: a first insulating fin; a second insulating fin; a nanostructure between the first insulating fin and the second insulating fin; and a gate structure wrapping around the nanostructure, a top surface of the gate structure disposed above a top surface of the first insulating fin, the top surface of the gate structure disposed below a top surface of the second insulating fin.

Transistor gate contacts and methods of forming the same

In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

Middle-of-line interconnect structure and manufacturing method

A semiconductor device includes a substrate, two semiconductor fins protruding from the substrate, an epitaxial feature over the two semiconductor fins and connected to the two semiconductor fins, a silicide layer over the epitaxial feature, a barrier layer over the silicide layer, and a metal layer over the barrier layer. The barrier layer includes a metal nitride. Along a boundary between the barrier layer and the metal layer, an atomic ratio of oxygen to metal nitride is about 0.15 to about 1.0.

Source/drain contact formation methods and devices

A titanium precursor is used to selectively form a titanium silicide (TiSi) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSiN) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.

Conductive structures and methods of formation

In method of manufacturing a semiconductor device, a source/drain epitaxial layer is formed, one or more dielectric layers are formed over the source/drain epitaxial layer, an opening is formed in the one or more dielectric layers to expose the source/drain epitaxial layer, a first silicide layer is formed on the exposed source/drain epitaxial layer, a second silicide layer different from the first silicide layer is formed on the first silicide layer, and a source/drain contact is formed over the second silicide layer.

Method of manufacturing a semiconductor device and a semiconductor device

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Conductive feature formation and structure

The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

Hybrid conductive structures

A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.

Dual side contact structures in semiconductor devices

A semiconductor structure includes an n-type epitaxial source/drain feature (NEPI) and a p-type epitaxial source/drain feature (PEPI) over a substrate, wherein a top surface of the NEPI is lower than a top surface of the PEPI. The semiconductor structure further includes a metal compound feature disposed on the top surface of the NEPI and the top surface of the PEPI. The metal compound feature extends continuously from the top surface of the NEPI to the top surface of the PEPI. The semiconductor structure further includes a contact feature disposed on the metal compound feature and a via structure disposed over the contact feature.

Source/drain EPI structure for improving contact quality

The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Selective formation of titanium silicide and titanium nitride by hydrogen gas control

Growing community of inventors

Hsinchu, Taiwan

Cheng-Wei Chang