United Microelectronics Corp.

Cheng-Tzung Tsai

Chen-Hua Tsai

Chien-Hung Chen

Chun-Yuan Wu

Yu-Ru Yang

Shih-Hsien Huang

Sheng-Hao Lin

Huai-Tzu Chiang

Wen-Tai Chiang

Hao-Ming Lee

Bang-Chiang Lan

Po-Wei Liu

Yu-Hsin Lin

Shih-Hung Tsai

Yi-Cheng Liu

Ching-I Li

Po-Jui Liao

Tzu-Yun Chang

Chia-Hsun Tseng

Tsung-Lung Tsai

Cheng-Chih Kung

Lien-Sheng Chung

Tzu-Feng Kuo

Tai-Yuan Li

A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.

Semiconductor device and manufacturing method thereof

Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

Fin-type field effect transistor and method of forming the same

A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

Semiconductor device and method for fabricating the same

A semiconductor structure includes a semiconductor substrate, a dielectric structure formed on the semiconductor substrate and including at least a recess formed therein, a fin formed in the recess, and a dislocation region formed in the fin. The semiconductor substrate includes a first semiconductor material. The fin includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. A topmost portion of the dislocation region is higher than an opening of the recess.

Semiconductor structure

A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.

Metal-gate CMOS device and fabrication method thereof

Metal-gate CMOS device

A method for manufacturing a semiconductor device is provided. A gate structure is formed on a substrate. A first dopant implantation and a first strain atom implantation are performed. Thereafter, spacers are formed on sidewalls of the gate structure. A second dopant implantation and a second strain atom implantation are performed. A solid-phase epitaxy annealing process is performed to form source and drain regions made of a semiconductor compound solid-phase epitaxial layer beside the gate structure.

Semiconductor device and method for manufacturing the same

A SiC region and a source/drain region are formed such that the SiC region includes a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region. The concentration of crystalline SiC in the second portion is higher than the concentration of crystalline SiC in the first portion. The SiC region may be formed through a normal implantation before the second spacer is formed, or the SiC region may be formed through a tilt implantation or deposition epitaxially in a recess having a sigma-shape like sidewall after the second spacer is formed.

Method of fabricating an NMOS transistor

A method of fabrication of a metal oxide semiconductor field effect transistor is disclosed. At first, a substrate on which a gate structure is formed is provided. Afterward, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a plurality of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

Metal oxide semiconductor field effect transistor with strained source/drain extension layer

A method of fabricating a CMOS transistor includes forming strained channels by re-crystallized amorphous polysilicon with the tensile film or the compressive film during annealing. C or Ge ions are optionally used to form solid-phase epitaxy to amplify the stress in the strained channel. Therefore, the charge carrier mobility in a CMOS transistor is improved.

Method of fabricating CMOS transistor

A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

Method of fabrication of metal oxide semiconductor field effect transistor

A method of manufacturing a metal oxide semiconductor is provided. The method includes forming an offset spacer and a disposable spacer around the offset spacer. Then, forming a plurality of epitaxial layers outside the disposable spacer and removing the disposable spacer. In addition, the method includes forming a plurality of source/drain extension areas in the substrate outside the offset spacer and the epitaxial layers. Because the source/drain extension areas are formed after the selective epitaxial growth process, the thermal of the selective epitaxial growth process does not damage the source/drain extension areas.

Method of manufacturing metal oxide semiconductor and complementary metal oxide semiconductor

The invention is directed to a method for forming a metal-oxide semiconductor field effect transistor. The method comprises steps of providing a substrate having a gate structure formed thereon, wherein a plurality of isolation structures are located in the substrate adjacent to both sides of the gate structure and then forming a first spacer on the sidewall of the gate structure. A portion of the substrate between the first spacer and the isolation structures is removed to form a recession and a source/drain layer is deposited in the recession, wherein the top surface of the source/drain layer is higher than the top surfaces of the isolation structures. A second spacer is formed on the isolation structures and at the sidewall of the source/drain layer and a metal silicide layer is formed on the source/drain layer.

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Taipei, Taiwan

Cheng-Tzung Tsai