United Microelectronics Corp.

Ememory Technology Inc.

Powerchip Semiconductor Corporation

Cheng-Tung Huang

Shyh-Fann Ting

Tzyy-Ming Cheng

Wen-Han Hung

Kun-Hsien Lee

Li-Shian Jeng

Jen-Yu Wang

Yi-Ting Wu

Po-Chun Yang

Yung-Ching Hsieh

Jian-Jhong Chen

Yu-Ming Lin

Meng-Yi Wu

Yi-Chung Sheng

Chia-Wen Liang

Yan-Jou Chen

Bo-Chang Li

Tzer-Min Shen

Wen-Yin Weng

Shih-Chieh Hsu

Sheng-Hao Lin

Ta-Kang Lo

Tsai-Fu Chen

Ya-Ru Yang

Yen-Wei Tung

Neng-Kuo Chen

Kuan-Yang Liao

Wei-Tsun Shiau

Jing-Chang Wu

Wei-Heng Hsu

Jhen-Siang Wu

Teng-Chun Tsai

Yu-Cheng Tung

Ching-Hsiang Hsu

Chien-Chung Huang

Jih-Wen Chou

Su Xing

Nien-Chung Li

Chih-Chiang Wu

Saysamone Pittikoun

Tsung-Han Lee

Chang-Chi Huang

Yi-Han Ye

Chih-Hsun Chu

Hsueh-Wen Wang

Shao-Ta Hsu

Leo Wang

Yi-Cheng Liu

Tzermin Shen

Chien-Yu Ko

Chun-Hsien Huang

Ching-Sung Yang

Yu-Tse Kuo

Jiunn-Ren Hwang

Shu-Ru Wang

Shu-Yen Chan

Tung-Hsing Lee

Chun-Yen Tseng

Bang-Chiang Lan

Tong-Hsin Lee

Tsai-Fu Hsiao

Tzu-Yun Chang

Jing-Yi Huang

Chang-Hung Chen

Chia-Wei Lee

Chih-Wei Tsai

Hsin-Chih Yu

Shih-Jung Tu

Yao-Chin Cheng

Ya-Lan Chiou

Chien-Hsing Lee

Da-Ching Chiou

Sun-Chin Wei

Min-Yi Chang

Chia-Wen Lang

Alex Liu

Wen-Chi Chen

Yi-Cheng Sheng

Zong-Sheng Zheng

Shih-Chien Hsu

Chin-Lan Chen

Chung-Min Shih

A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.

MRAM circuit structure and layout structure

A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Sense amplifier circuit with temperature compensation

A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

Bottom-pinned spin-orbit torque magnetic random access memory and method of manufacturing the same

A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.

Magnetic memory device having shared source line and bit line

A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.

Semiconductor device

In an MRAM, each unit cell includes two non-volatile storage units, three N-type transistors and three P-type transistors. Each N-type transistor is coupled in parallel with a corresponding P-type transistor for forming a transmission gate which provides bi-directional current, thereby preventing source degeneration.

Magnetoresistive random-access memory

A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.

Method of making FinFET CMOS device including single diffusion break in each of NMOS and PMOS regions

A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.

Layout pattern for magnetoresistive random access memory

A memory includes (n&#x2212;1) non-volatile cells, (n&#x2212;1) bit lines and a current driving circuit. Each of the (n&#x2212;1) non-volatile cells includes a first terminal and a second terminal. An ith bit line of the (n&#x2212;1) bit lines is coupled to a first terminal of an ith non-volatile cell of the (n&#x2212;1) non-volatile cells. The current driving circuit includes n first transistors coupled to the (n&#x2212;1) non-volatile cells.

Memory including non-volatile cells and current driving circuit

A first MRAM set includes a first transistor and a second transistor. The first transistor includes a first gate structure, a first source/drain doping region and a first common source/drain doping region. The second transistor includes a second gate structure, a second source/drain doping region and the first common source/drain doping region. A second MTJ is disposed on the second transistor. The first common source/drain doping region electrically connects to the second MTJ. A first MTJ is disposed on the first transistor. The sizes of the first MTJ and the second MTJ are different. The second MTJ connects to the first MTJ in series. A bit line electrically connects the first MTJ. A source line electrically connects to the first source/drain doping region and the second source/drain doping region.

2-transistor 2-magnetic tunnel junction (2T2MTJ) MRAM structure

FinFET CMOS device including single diffusion break in each of NMOS and PMOS regions

A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.

Method of forming fin shape structure having different buffer layers

A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.

Transistor and manufacturing method thereof

Growing community of inventors

Kaohsiung, Taiwan

Cheng-Tung Huang