United Microelectronics Corp.

Molex Corporation

Molex Incorproated

Cheng-Te Lin

Min-Chih John Hsuan

Tien-Hao Tang

Li-Cih Wang

An electrostatic discharge device includes a substrate. A deep doped well of a first conductive type is disposed in the substrate. A drain doped well of the first conductive type is disposed in the substrate above the deep doped well. An inserted doping well of a second conductive type is disposed in the drain doped well, in contact with the deep doped well. A drain region of the first conductive type is in the drain doped well and above the inserted doping well. An inserted drain of the second conductive type is on the inserted doping well and surrounded by the drain region. A source doped well of the second conductive type is disposed in the substrate, abut the drain doped well. A source region is disposed in the source doped well. A gate structure is disposed on the substrate between the drain region and the source region.

Electrostatic discharge device

A wafer level package structure. The method of forming the wafer level package structure includes covering a silicon chip having a plurality of integrated circuit devices thereon with an insulation layer. Next, a plurality of bonding pads is formed on the periphery of the silicon chip above the insulation layer. The bonding pads are formed such that each bonding pad is electrically connected to the terminal of an integrated circuit device. Thereafter, a passivation layer is deposited over the insulation layer and the bonding pads, and then openings that expose a portion of the bonding pad are formed. Subsequently, a metallic layer is formed on the sidewalls and the exposed bonding pad area. The metallic layer also extends over the passivation layer in the neighborhood of the opening and towards the edge of the wafer chip. Next, a layer of packaging material is deposited over the passivation layer. Finally, a metallic bump is formed over the exposed metallic layer lying above each opening.

Wafer level package

A face-to-face multi-chip package comprises a lead frame comprising at least a die pad and a plurality of leads, wherein the leads further comprise a plurality of inner leads and a plurality of outer leads. The package further comprises at least three chips, each having a surface comprising a plurality of pads. The chips are disposed with the surfaces comprising the pads face to face. A plurality of bumps are disposed on some of the pads to electrically connect the chips. A plurality of electrical conductors connects predetermined ones of the pads to the inner leads; and an insulation material fully or partially seals the die pad, the chips and the inner leads.

Face-to-face multi-chip package

A multi-chip chip scale package. The package has a film carrier whereby two chips with different sizes can be disposed on the same film carrier. A flip chip technique is used to arrange each chip on each side of the film carrier face to face. A bump is formed on each chip to electrically connect with the film carrier. An insulation material is filled in between the chips to leave one side of each chip exposed. The conductive wires of the film carrier are connected to the chips directly.

Multi-chip chip scale package

A multi-chip chip scale package. A film carrier is in use. Two chips with different sizes can be disposed on the same film carrier. The flip chip technique is used to arrange each chip on each side of the film carrier face to face. A bump is formed on each chip to electrically connect with the film carrier. An insulation material is infilled between the chips to leave one side of each chip exposed. The conductive wires of the film carrier are connected with the chip directly without going through other carrier.

A shielded electrical connector includes a housing formed as a generally rectangular unitary hollow block made of an insulator material, and a shielding member made from a punched conductive metal blank is mounted on the housing to provide protection against electromagnetic interference. Conductive latches for engaging a shield of a mating connector extend along and are supported by side wall portions of the shield.

Shielded electrical connector

An electrical connector includes a dielectric connector body which is formed with vertically aligned upper and lower terminal holes. A tail guiding part projects rearwardly from a rear side of the connector body adjacent to a bottom side thereof and is formed with a tail guiding slot for passage of the downwardly extending tail portions of upper and lower terminals which are mounted in the upper and lower terminal holes, respectively. The tail guiding part has a pair of vertically stepped guide walls that confine a narrow and a wide section in the tail guiding slot and that provide shoulder faces between the two sections. The tail portion of the upper terminal has an enlarged part to contact against the shoulder faces, thereby preventing the tail portion of the upper terminal from moving toward the tail portion of the lower terminal. A portion of the tail guiding part is upset to form projections that extend into the wide section of the tail guiding slot to clamp the tail portion of the upper terminal against the shoulder faces.

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Taipei Hsien, Taiwan

Cheng-Te Lin