Taiwan Semiconductor Manufacturing Comp. Ltd.

Cheng-Te Chang

Yi-Kan Cheng

Chin-Yuan Huang

Chih Ming Yang

Chau-Wen Wei

A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.

Method and apparatus for modeling multi-terminal MOS device for LVS and PDK

An apparatus comprises two n-type metal oxide semiconductor (MOS) devices formed next to each other. Each n-type MOS device further includes a pair of face-to-face diodes formed in an isolation ring. A method of modeling the apparatus comprises reusing four-terminal MOS device models in standard cell libraries and combining the four-terminal MOS device model and the isolation ring model into a 4T MOS plus isolation ring model. The method of modeling the apparatus further comprises adding a dummy device between a body contact of the first n-type MOS device and a body contact of the second n-type MOS device.

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Hsin-Chu, Taiwan

Cheng-Te Chang