Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

United Microelectronics Corp.

Tamkang University

Unik World Industrial Co., Ltd.

Cheng-Hsien Chou

Sheng-Chau Chen

Cheng-Yuan Tsai

Wen-San Chou

Yeur-Luen Tu

Sheng-Chan Li

Kuo-Ming Wu

Chih-Yu Lai

Chih-Hui Huang

Shih Pei Chou

Jiech-Fun Lu

Chih-Hao Yu

Chien-Ting Lin

Yung-Lung Lin

Tsun-Kai Tsao

Che-Hua Hsu

Li-Wei Cheng

Ming-Che Lee

Tian-Fu Chiang

Chien-Ming Lai

Yi-Wen Chen

Guang-Hwa Ma

Hau-Yi Hsiao

Min-Feng Kao

Chia-Shiung Tsai

Hsiao-Hui Tseng

Yen-Ting Chiang

Kuo-Hwa Tzeng

I-Nan Chen

Wen-I Hsu

Yi-Ming Lin

Chao-Ching Chang

Zhi-Yang Wang

Keng-Yu Chou

Shih-Pei Chou

Dun-Nian Yaung

Ching-Chun Wang

Tzu-Hsuan Hsu

Shyh-Fann Ting

Chun-Wei Chang

Yen-Chang Chu

Min-Ying Tsai

Wei-Cheng Hsu

Kai-Chun Hsu

Jung-Tsung Tseng

Cheng-Han Lin

Yen-Chang Chen

Chih-Ta Chen

Yen-Ting Chou

Yu-Jen Wang

Feng-Chi Hung

Tzu-Jui Wang

Hung-Ling Shih

Tzu-Hsiang Chen

Min-Hui Lin

Ming-Huei Shen

Tsung-Wei Huang

Chun-Hsien Lin

Chin-Fu Lin

Keng-Ying Liao

Nien-Ting Ho

Ching-Chung Su

Hung-Wen Hsu

Po-Zen Chen

Yi-Hung Chen

Chung-Bin Tseng

I-Nan Lin

Jin-Hua Huang

Ming-Jhe Lee

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a mask layer on a first side of a semiconductor substrate. The mask layer comprises a plurality of sidewalls defining a plurality of openings. A first etch process is performed on the semiconductor substrate to form a plurality of recesses within the semiconductor substrate. A second etch process is performed on the semiconductor substrate to expand the plurality of recesses and form a plurality of protrusions that comprise curved opposing sidewalls.

Absorption enhancement structure to increase quantum efficiency of image sensor

In some embodiments, the present disclosure relates to an image sensor. The image sensor comprises a substrate. A photodetector is in the substrate and includes a semiconductor guard ring extending into a first side of the substrate. A shallow trench isolation (STI) structure extends into the first side of the substrate. An outer isolation structure extends into a second side of the substrate, opposite the first side of the substrate, to the STI structure. The STI structure and the outer isolation structure laterally surround the photodetector. An inner isolation structure extends into the second side of the substrate and overlies the photodetector. The inner isolation structure is vertically separated from the photodetector by the substrate. Further, the outer isolation structure laterally surrounds the inner isolation structure.

Image sensor with dual trench isolation structure

A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating. wherein the composite etch stop mask layer includes a silicon nitride layer and a stressed layer. A percentage of Si—H bonds in the silicon nitride layer is greater than a percentage of Si—H bonds in the stressed layer.

Composite etch stop layers for sensor devices

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having a first horizontally extending surface and a second horizontally extending surface above the first horizontally extending surface as viewed in a cross-sectional view. The first horizontally extending surface continuously wraps around an outermost perimeter of the second horizontally extending surface in a closed loop as viewed in a plan-view. A second substrate is disposed over the first substrate and includes a third horizontally extending surface above the second horizontally extending surface as viewed in the cross-sectional view. The second horizontally extending surface continuously wraps around an outermost perimeter of the third horizontally extending surface in a closed loop as viewed in the plan-view.

Techniques for wafer stack processing

A thin-film deposition system includes a top plate positioned above a wafer and configured to generate a plasma during a thin-film deposition process. The system includes a gap sensor configured to generate sensor signals indicative of a gap between the wafer and the top plate. The system includes a control system configured to adjust the gap during the thin-film deposition process responsive to the sensor signals.

Method and system for adjusting the gap between a wafer and a top plate in a thin-film deposition process

The present disclosure for wafer bonding, including forming an epitaxial layer on a top surface of a first wafer, forming a sacrificial layer over the epitaxial layer, trimming an edge of the first wafer, removing the sacrificial layer, forming an oxide layer over the top surface of the first wafer subsequent to removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer.

Method for wafer bonding including edge trimming

An air stop sheet of a piston of a cylinder, the piston is accommodated in an air compressor, and an air stop sheet is accommodated on a head of the piston. The air stop sheet includes a bending section having a positioning zone and an acting zone and configured to be a boundary line of the acting zone and the positioning zone. The acting zone backing the cylinder turns on relative to the plane of the head at an open angle θ, thus producing an air flowing space. A piston rod extends downward from the head and includes a cavity, an air conduit, a column, and a spring configured to abut against the acting zone of the air stop sheet. The air stop sheet is pushed by the spring to turn on at an open angle θ, and the air conduit and the air channel communicate with atmosphere.

Air stop sheet of piston of cylinder

The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.

Multi-wafer capping layer for metal arcing protection

The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a pixel region arranged between one or more trenches formed by sidewalls of the substrate. One or more dielectric materials are arranged along the sidewalls of the substrate forming the one or more trenches. A conductive material is disposed within the one or more trenches. The conductive material is electrically coupled to an interconnect disposed within a dielectric arranged on the substrate.

Image sensor scheme for optical and electrical improvement

A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.

Semiconductor structure, back-side illuminated image sensor and method for manufacturing the same

Various embodiments of the present disclosure are directed towards a pixel sensor. The pixel sensor includes a substrate having a front-side opposite a back-side. An image sensor element comprises an active layer disposed within the substrate, where the active layer comprises germanium. An anti-reflective coating (ARC) structure overlies the back-side of the substrate. The ARC structure includes a first dielectric layer overlying the back-side of the substrate, a second dielectric layer overlying the first dielectric layer, and a third dielectric layer overlying the second dielectric layer. A first index of refraction of the first dielectric layer is less than a second index of refraction of the second dielectric layer, and a third index of refraction of the third dielectric layer is less than the first index of refraction.

Dielectric structure overlying image sensor element to increase quantum efficiency

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure includes a plurality of interconnects disposed within a dielectric structure. A dielectric protection layer is along a sidewall of the interconnect structure and along a sidewall and a recessed surface of the substrate. A bottommost surface of the dielectric protection layer rests on the recessed surface of the substrate.

Trim wall protection method for multi-wafer stacking

Air compressor

A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

Deep trench isolations and methods of forming the same

Growing community of inventors

Tainan, Taiwan

Cheng-Hsien Chou