United Microelectronics Corp.

Cheng H Huang

Water Lur

Gary Y Hong

Hong-Tsz Pan

Ming-Tzong Yang

Ben Chen

A method of forming a field oxide isolation region is described, in which a masking layer is formed over a silicon substrate. The masking layer is patterned to form an opening for the field oxide isolation region, whereby the remainder of the masking layer forms an implant mask. A conductivity-imparting dopant is implanted through the opening into the silicon substrate. Oxygen is implanted through the opening into the silicon substrate in multiple implantation steps. The implant mask is removed. The field oxide isolation region is formed in and on the silicon substrate, by annealing in a non-oxygen ambient. Alternately, the field oxide isolation region is formed by annealing in oxygen, simultaneously forming a gate oxide in the region between the field oxide isolation regions.

Field oxidation by implanted oxygen (FIMOX)

A method for forming MOSFET devices, with an improved polycide gate has been accomplished. The polycide structure, made with metal silicide on polysilicon has a reduced rate of adhesion loss or peeling of the metal silicide from the underlying polysilicon, due to the unique surface of the polysilicon. The desired surface of the polysilicon, that will reduce the peeling phenomena, is a wavy or undulated surface. This is accomplished by either depositing the polysilicon at conditions that result in a hemi-spherical grained surface, or obtaining a similar wavy or undulated surface by treating smooth polysilicon in either phosphoric acid or by anodization in hydrofluoric acid. The adhesion of the subsequent metal silicide to the wavy surface of the polysilicon is improved to a point where peeling of the metal silicide from the underlying polysilicon is eliminated.

Method to eliminate polycide peeling

A method for fabricating a stacked storage capacitor on a dynamic random access memory (DRAM) cell with increased capacitance was accomplished. The stacked capacitor is used with a field effect transistor (FET) as part of a dynamic random access memory (DRAM) cell for storing data in the form of stored charge on the capacitor. The method for making the capacitor involves forming a bottom electrode from a single polysilicon layer having a fin-shaped structure, and then using a second polysilicon layer and a plasma etch back to create a second self-aligned fin-like structure that significantly increases the surface area of the capacitor bottom electrode. The capacitor structure is then completed by forming a thin capacitor dielectric layer on the bottom electrode and depositing a third polysilicon layer to form the top electrode and complete the capacitor with significantly increased capacitance and an economy of processing steps.

method of manufacturing a new DRAM capacitor structure having increased

A new method of forming a contact opening by using a sacrificial spin-on-glass layer is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A glasseous layer is deposited over the uneven surface of the substrate and reflowed at low temperature whereby the glasseous layer will have a trench shaped surface over the planned contact opening area. The glasseous layer is covered with a spin-on-glass layer wherein the spin-on-glass planarizes the surface of the substrate. The spin-on-glass layer is baked and then covered with a uniform thickness layer of photoresist. The photoresist layer is exposed and developed to form the desired photoresist mask for the contact opening. The exposed spin-on-glass and glasseous layers are etched away to provide the contact opening to the semiconductor substrate. The photoresist layer is stripped and the sacrificial spin-on-glass layer is removed to complete the formation of the contact opening in the manufacture of the integrated circuit.

Process for contact hole formation using a sacrificial SOG layer

A method of forming a self-aligned trenched contact in the fabrication of an integrated circuit is described. Semiconductor device regions are formed in and on a semiconductor substrate wherein the semiconductor device regions include gate electrodes on the surface of the semiconductor substrate and source/drain regions within the semiconductor substrate. Spacers are formed on the sidewalls of the gate electrodes. A layer of silicon oxide is deposited over the surface of the substrate wherein the silicon oxide contacts the source/drain regions within the substrate between the gate electrodes. The substrate is covered with a layer of photoresist which is patterned to provide an opening over the planned self-aligned trenched contact between the gate electrodes. The silicon oxide is etched away to provide an opening to the silicon substrate using the patterned photoresist and the sidewall spacers as a mask. A trench is etched into the silicon substrate within the opening using the photoresist and the sidewall spacers as a mask to form the self-aligned trenched contact opening. A conducting layer is deposited within the trenched opening to complete the contact in the manufacture of the integrated circuit device.

Self-aligned trenched contact (satc) process

A method is described for fabricating an integrated circuit in which the gate electrodes and gate dielectric silicon oxide are protected from electrical charge damage during ion implantation. A thin conducting layer is deposited over the pattern of gate electrodes/gate dielectric silicon oxide wherein the conducting layer is grounded to the silicon substrate. The high-dose ion implantation is applied through the conducting layer which layer grounds the electrical charge resulting from the ion implantation, and hence protects the gate electrodes from charge damage. The electron 'flood gun' need not be used.

Charge damage free implantation by introduction of a thin conductive

A new method of local oxidation using a multiple process is described. A thin silicon oxide layer is formed over the surface of a silicon substrate. A layer of silicon nitride is deposited overlying the silicon oxide layer. The silicon oxide and silicon nitride layers are patterned to provide openings of the smallest size exposing portions of the silicon substrate to he oxidized and growing field oxide regions within these smallest size openings. The patterning and growing of field oxide regions is repeated for each larger size of opening required. The silicon nitride and silicon oxide layers are removed, thereby completing local oxidation of the integrated circuit.

Multi-LOCOS (local oxidation of silicon) isolation process

A new method of local oxidation by means of stress-releasing narrow trenches is described. Pad silicon oxide, silicon nitride, and silicon dioxide layers are formed on a silicon substrate. Portions of these layers not covered by a mask are etched away to provide an opening to the silicon substrate where the field oxidation region is to be formed. The silicon substrate is etched into where it is exposed to form a shallow trench within the opening. Silicon dioxide spacers and silicon nitride spacers are formed on the sidewalls of the opening. The silicon substrate is coated with a spin-on-glass layer. The spin-on-glass layer is cured, then etched back so that the spin-on-glass layer remains only within the shallow trench not covered by the spacers. The silicon nitride spacers are stripped away. Narrow trenches are etched into the silicon substrate under the silicon nitride spacers. The silicon dioxide spacers and spin-on-glass layer are removed leaving the opening entirely exposed. Channel-stops are selectively ion implanted through the opening into the substrate underneath the trenches. The silicon substrate is oxidized within the opening wherein the silicon substrate is transformed to silicon dioxide and wherein the silicon dioxide expands to fill the narrow trenches. The narrow trenches act to relieve stress within the silicon substrate. The silicon dioxide expands vertically to provide a fully recessed surface of the field oxidation region.

Locos technology with narrow silicon trench

A new method of local oxidation using a nitrogen implant through a spin-on-glass film is described. A thin silicon oxide layer is formed over the surface of a silicon substrate. A layer of silicon nitride is deposited overlying the silicon oxide layer. The silicon oxide and silicon nitride layers are patterned to provide openings of various sizes exposing portions of the silicon substrate to be oxidized. Ions are selectively implanted into the silicon substrate through the openings. The patterned surface of the substrate is covered with a spin-on-glass material. The spin-on-glass material is thicker within the smaller openings and thinner within the larger openings. The spin-on-glass material is soft-baked. Nitrogen ions are selectively implanted into the silicon substrate through the spin-on-glass material within the openings wherein fewer nitrogen ions are implanted through the thicker spin-on-glass material within the smaller openings and more nitrogen ions are implanted through the thinner spin-on-glass material within the larger openings. The spin-on-glass material is removed. Field oxide regions are grown within the openings wherein the rate of field oxidation is inhibited most within the openings through which a larger concentration of nitrogen ions were implanted and inhibited to a lesser extent in openings through which smaller concentrations of nitrogen ions were implanted resulting in nearly equal thicknesses of field oxide regions in all openings of various sizes.

Uniform field oxidation for locos isolation

A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the peeling problems of refractory metal silicide layers on a polycide gate. The process of this invention has been simplified by not using several of the high thermal cycle process steps believed to be necessary for successfully making a polycide gate lightly doped drain MOS FET integrated circuit. These steps are (1) the thermal oxidation after the polycide etching step, (2) the densification step after the blanket deposition of silicon dioxide layer for the spacer preparation, and (3) the silicon oxide capping of the refractory metal silicide layer after the spacer formation by anisotropically etching. The result is a process that provides a non-peeling polycide gate lightly doped drain MOS FET integrated circuit device.

Growing community of inventors

Hsin-Chu, Taiwan

Cheng H Huang