United Microelectronics Corp.

Cheng-Guo Chen

Chien-Ting Lin

Ssu-I Fu

Zhi-Cheng Lee

Che-Hua Hsu

Shao-Hua Hsu

Yu-Hsiang Hung

Chung-Fu Chang

Ta-Kang Lo

Kun-Yuan Wu

Hung-Ling Shih

Po-Kang Yang

Tai-You Chen

Chiu-Sheng Ho

En-Chiuan Liou

Chan-Lon Yang

Po-Chao Tsao

I-Ming Tseng

Chih-Wei Yang

Rai-Min Huang

Yi-Wen Chen

Shin-Chi Chen

Po-Jui Liao

Jie-Ning Yang

Jian-Cun Ke

Guang-Yaw Hwang

Tsung-Lung Tsai

Jung-Tsung Tseng

Kun-Yuan Lo

Teng-Chun Tsai

Yi-Wei Chen

Chun-Hsien Lin

Chin-Cheng Chien

Shih-Fang Tzou

Chun-Yuan Wu

Jiunn-Hsiung Liao

Chia-Lin Hsu

Cheng-Han Wu

Hsin-Fu Huang

Wen-Han Hung

Chien-Ming Lai

Min-Chuan Tsai

Po-Cheng Huang

Chiu-Hsien Yeh

Tong-Jyun Huang

Chia-Jui Liang

Ying-Tsung Chen

Tzung-Ying Lee

Huan-Chi Ma

Hung-Yi Wu

Kuo-Yu Liao

Chien-Wen Yu

Jun-Jie Wang

Shang-Jr Chen

Cheng-Yu Ma

Zhi-Jian Wang

Heng-Ching Huang

Jian-Li Lin

Kuan-Ting Lu

Wei-Da Lin

Yi-Chuan Chen

A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

MOS capacitor and fabrication method thereof

A high-electron mobility transistor includes a substrate, a gate electrode, a drain electrode, a source electrode and a first field plate. The substrate includes an active region. The gate electrode is disposed on the substrate. The drain electrode is disposed at one side of the gate electrode. The source electrode is disposed at another side of the gate electrode. The first field plate is electrically connected with the source electrode and extends from the source electrode toward the drain electrode. An overlapping area of the first field plate and the gate electrode is smaller than an overlapping area of the gate electrode and the active region.

High-electron mobility transistor and method for fabricating the same

A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

Method of fabricating tunneling transistor

Tunneling transistor and method of fabricating the same

First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.

Method for fabricating semiconductor device

A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An Oambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

Oxygen treatment of replacement work-function metals in CMOS transistor gates

A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

Semiconductor device with epitaxial structure

A method for fabricating a field-effect transistor is provided. The method includes: forming a gate dielectric layer and a barrier layer on a substrate in sequence; forming a first silicon layer on and in contact with the barrier layer; performing a thermal treatment to form a silicide layer between the barrier layer and the first silicon layer; and forming a second silicon layer on and in contact with the first silicon layer.

Field-effect transistor and fabricating method thereof

A field-effect transistor comprises a substrate, a gate dielectric layer, a barrier layer, a metal gate electrode and a source/drain structure. The gate dielectric layer is disposed on the substrate. The barrier layer having a titanium-rich surface is disposed on the gate dielectric layer. The metal gate electrode is disposed on the titanium-diffused surface. The source/drain structure is formed in the substrate and adjacent to the metal gate electrode.

A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

Replacement gate process and device manufactured using the same

A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and a gate structure partially overlapping the fin-shaped structure is formed. Subsequently, a dielectric layer is blanketly formed on the substrate, and a part of the dielectric layer is removed to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure. Furthermore, the second spacer and a part of the fin-shaped structure are removed to form at least a recess at a side of the gate structure, and an epitaxial layer is formed in the recess.

Semiconductor process

A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, wherein the first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

Semiconductor device and fabrication method thereof

A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure in the substrate; forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure; forming a first gate structure on the STI and the fin-shaped structure; and removing a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure.

Fin-shaped field-effect transistor (FinFET)

An epitaxial process includes the following steps. A first gate and a second gate are formed on a substrate. Two first spacers are formed on the substrate beside the first gate and the second gate respectively. Two first epitaxial layers having first profiles are formed in the substrate beside the two first spacers respectively. A second spacer material is formed to cover the first gate and the second gate. The second spacer material covering the second gate is etched to form a second spacer on the substrate beside the second gate and expose the first epitaxial layer beside the second spacer while reserving the second spacer material covering the first gate. The exposed first epitaxial layer in the substrate beside the second spacer is replaced by a second epitaxial layer having a second profile different from the first profile.

Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures

The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.

Method of manufacturing semiconductor device having metal gates

Growing community of inventors

Changhua County, Taiwan

Cheng-Guo Chen