Yangtze Memory Technologies Co., Ltd.

Cheng Gan

Wei Liu

Liang Chen

Shunfu Chen

Xin Wu

Zhiliang Xia

Wenxi Zhou

Kun Zhang

Yuancheng Yang

Yanhong Wang

Yanwei Shi

Shi Qi Huang

Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.

Structure and method for forming capacitors for a three-dimensional NAND

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recess gate transistor is formed on a second substrate. The recess gate transistor includes a recess gate structure protruding into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.

Peripheral circuit having recess gate transistors and method for forming the same

Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the 3D memory device includes a peripheral circuitry formed on a first substrate. The peripheral circuitry includes a plurality of peripheral devices on a first side of the first substrate, a first interconnect layer, and a deep-trench-isolation on a second side of the first substrate, wherein the first and second sides are opposite sides of the first substrate and the deep-trench-isolation is configured to provide electrical isolation between at least two neighboring peripheral devices. The 3D memory device also includes a memory array formed on a second substrate. The memory array includes at least one memory cell and a second interconnect layer, wherein the second interconnect layer of the memory array is bonded with the first interconnect layer of the peripheral circuitry, and the peripheral devices are electrically connected with the memory cells.

Structure and method for isolation of bit-line drivers for a three-dimensional NAND

A capacitor is provided. The capacitor includes a substrate, at least two conductive plates formed in the substrate and extending into the substrate, at least one insulating structure formed between two adjacent conductive plates of the at least two conductive plates and extending into the substrate, and a plurality of contacts, each extending into respective one of the at least two conductive plates.

Capacitor structure and method of forming the same

In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit including a recess gate transistor. The peripheral circuits also include a second peripheral circuit including a flat gate transistor.

In a method for manufacturing a semiconductor device, a doped region is formed in a substrate from a first main surface. An insulating layer is formed over the doped region of the substrate. Contacts are formed in the insulating layer such that the contacts extend into the doped region. A portion of the substrate is removed from a second main surface. A trench, a first conductive line, and a second conductive line are formed from the doped region of the substrate through etching the substrate from the second main surface. The trench extends through the substrate to expose the insulating layer. The first and second conductive lines are spaced apart from each other by the trench. The contacts are positioned along and in contact with the first and second conductive lines. The trench is filled with a dielectric material.

Local word line driver device, memory device, and fabrication method are provided. A local word line driver device includes a substrate and an array of transistor structures formed on the substrate. The transistor structures are configured in rows and columns. The substrate includes a plurality of first field regions each between adjacent rows of the transistor structures, and a plurality of second field regions each between adjacent columns of the transistor structures. A deep trench isolation structure is formed in at least one field region of: the plurality of first field regions or the plurality of second field regions, of the substrate.

Local word line driver device, memory device, and fabrication method thereof

A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a plurality of semiconductor device arrays and forming a first interconnect layer on the plurality of semiconductor device arrays. The method also includes forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method further includes bonding the first and second interconnect layers and forming one or more isolation trenches through a second side of the first substrate that is opposite to the first side to expose a portion of the first side of the first substrate. The one or more isolation trenches are formed between first and second semiconductor device arrays of the plurality of semiconductor devices arrays. The method further includes disposing an isolation material to form one or more isolation structures respectively in the one or more isolation trenches.

Backside deep isolation structures for semiconductor device arrays

A capacitor is provided. The capacitor includes a substrate that has opposing first and second main surfaces. The capacitor also includes at least two conductive plates that are formed in the substrate and extend from the first main surface to the second main surface of the substrate. The capacitor further includes at least one insulating structure that is formed between two adjacent conductive plates of the at least two conductive plates and extends from the first main surface to the second main surface.

A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a plurality of semiconductor devices including at least first and second semiconductor devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the semiconductor devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes connecting the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.

Three-dimensional memory devices with backside isolation structures

A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a peripheral circuitry including first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes bonding the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.

Growing community of inventors

Hubei, China

Cheng Gan