Taiwan Semiconductor Manufacturing Comp. Ltd.

Comp-any Gmbh

Cheng-Chi Chuang

Chih-Hao Wang

Li-Zhen Yu

Lin-Yu Huang

Huan-Chieh Su

Chia-Hao Chang

Yu-Ming Lin

Chun-Yuan Chen

Kuan-Lun Cheng

Tai-I Yang

Tien-Lu Lin

Yi-Hsun Chiu

Chia-Tien Wu

Sheng-Tsung Wang

Jiann-Tyng Tzeng

Ching-Wei Tsai

Shang-Wen Chang

Wei-Cheng Lin

Shih-Chuan Chiu

Chih-Ming Lai

Chih-Liang Chen

Shih-Wei Peng

Yung-Chih Wang

Lo-Heng Chang

Ru-Gun Liu

Charles Chew-Yuen Young

Pei-Yu Wang

Kam-Tou Sio

Hui-Ting Yang

Hsin-Ping Chen

Yu-Xuan Huang

Kun-Ming Huang

Kuo-Cheng Chiang

Yung-Hsu Wu

Shun Li Chen

Wei-Chen Chu

Ming-Yi Lin

Meng-Huan Jao

Hsuan-Hui Hung

Hui-Zhong Zhuang

Shi Ning Ju

Zhi-Chang Lin

Guo-Huei Wu

Hsiang-Wei Liu

Kuan-lun Cheng

Lei-Chun Chou

Li-Lin Su

Yu-Chieh Liao

Chia-Lin Chuang

Tien-I Bao

Hai-Ching Chen

Sung-Li Wang

Hsin-Yen Huang

Yi-Hsiung Lin

Chi-Lin Teng

Wei-An Lai

Ting-Ya Lo

Chien Wen Lai

Hsiang-Lun Kao

Jian-Hua Chen

Ethan Hsiao

Wayne Lai

Kuo-Nan Yang

Jia-Chuan You

Shin-Yi Yang

Cheng-Ting Chung

Shuen-Shin Liang

Chia-Hung Chu

Yi-Bo Liao

Jin Cai

Po-Chin Chang

Kuo-cheng Chiang

Lipen Yuan

Fu-Hsiung Yang

Yuting Cheng

Tzu Pei Chen

Chao-Wei Tseng

Chiao-Hao Chang

Yun-Ju Fan

A method includes forming a gate electrode and a source/drain region over a bulk portion of a semiconductor substrate, forming a cut-metal-gate region to separate the gate electrode into a first portion and a second portion, forming a source/drain contact plug overlapping and electrically connected to the source/drain region, forming a first contact rail overlapping a portion of the cut-metal-gate region, removing the bulk portion of the semiconductor substrate, and etching the cut-metal-gate region to form a trench. A surface of the first contact rail is revealed to the trench. A via rail is formed in the trench, and the via rail is electrically connected to the source/drain region through the first contact rail.

Semiconductor structure with contact rail and method for forming the same

An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.

Integrated circuit structure with backside via rail

A semiconductor structure includes first and second epitaxial features, at least one semiconductor channel layer connecting the first and second epitaxial features, and a gate structure engaging the semiconductor channel layer. The first and second epitaxial features, the semiconductor channel layer, and the gate structure are at a frontside of the semiconductor structure. The semiconductor structure also includes a backside metal wiring layer at a backside of the semiconductor structure, and a backside conductive contact electrically connecting the first epitaxial feature to the backside metal wiring layer. The backside metal wiring layer is spaced away from the gate structure with an air gap therebetween.

Semiconductor device with air gaps and method of fabrication thereof

Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.

Semiconductor devices including low-k metal gate isolation and methods of fabrication thereof

A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Dual side contact structures for source/drain regions in semiconductor transistor devices and method of forming

A method for forming a semiconductor transistor device includes forming a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The channel structure is formed by forming a stack of semiconductor layers. The gate structure is formed wrapping around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are formed on opposite endings of the channel structure. The gate contact is formed on the gate structure. The back-side source/drain contact is formed under the first source/drain epitaxial structure. The second source/drain epitaxial structure is formed to have a concave bottom surface.

Drain side recess for back-side power rail device

Semiconductor device including a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

Semiconductor transistor devices having double-sided interconnect structures

A semiconductor structure includes a source/drain; one or more channel layers connected to the source/drain; a gate structure adjacent the source/drain and engaging each of the one or more channel layers; a first silicide layer over the source/drain; a source/drain contact over the first silicide layer; a power rail under the source/drain; one or more first dielectric layers between the source/drain and the power rail; and one or more second dielectric layers under the first silicide layer and on sidewalls of the source/drain, wherein the one or more second dielectric layers enclose an air gap.

Semiconductor devices with backside power rail and backside self-aligned via

A method includes forming a transistor over a substrate; forming a front-side interconnection structure over the transistor; after forming the front-side interconnection structure, removing the substrate; after removing the substrate, forming a backside via to be electrically connected to the transistor; depositing a dielectric layer to cover the backside via; forming an opening in the dielectric layer to expose the backside via; forming a spacer structure on a sidewall of the opening; after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and after forming the conductive feature, forming an air gap in the spacer structure.

Integrated circuit structure with backside interconnection structure having air gap

Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line in a direction parallel to a backside surface of the first dielectric layer.

Spacers for semiconductor devices including backside power rails

A semiconductor structure is provided, and includes a first fin structure, a second fin structure, and a third fin structure over a substrate. The second fin structure is located between the first fin structure and the third fin structure. The semiconductor structure also includes a fin isolation structure formed between the first fin structure and the third fin structure; and a gate structure formed over the first fin structure, the second fin structure, the third fin structure and the fin isolation structure. The semiconductor structure further includes a plurality of epitaxial structures formed over the first fin structure, the second fin structure and the third fin structure. The semiconductor structure includes a dielectric material over the first epitaxial structure, the second epitaxial structure, and the third epitaxial structure; and a contact formed in the dielectric material and connected to the first epitaxial structure and the third epitaxial structure.

Semiconductor structure and method for forming the same

Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure.

Semiconductor device having backside via and method of fabricating thereof

A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.

Air spacer and capping structures in semiconductor devices

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first conductive structure disposed over the device, and the first conductive structure includes a first sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer disposed on the first portion, a second conductive structure disposed adjacent the first conductive structure, and the second conductive structure includes a second sidewall having a third portion and a fourth portion. The semiconductor device structure further includes a second spacer layer disposed on the third portion, and an air gap is formed between the first conductive structure and the second conductive structure. The second portion, the first spacer layer, the fourth portion, and the second spacer layer are exposed to the air gap.

Semiconductor device structure and methods of forming the same

A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

Method for forming long channel back-side power rail device

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Taipei, Taiwan

Cheng-Chi Chuang