Taiwan Semiconductor Manufacturing Comp. Ltd.

Comp-any Gmbh

Cheng-Chi Chuang

Chih-Hao Wang

Li-Zhen Yu

Lin-Yu Huang

Huan-Chieh Su

Chia-Hao Chang

Yu-Ming Lin

Chun-Yuan Chen

Kuan-Lun Cheng

Tai-I Yang

Tien-Lu Lin

Chia-Tien Wu

Sheng-Tsung Wang

Jiann-Tyng Tzeng

Yi-Hsun Chiu

Chih-Ming Lai

Chih-Liang Chen

Wei-Cheng Lin

Shih-Chuan Chiu

Ching-Wei Tsai

Shang-Wen Chang

Yung-Chih Wang

Shih-Wei Peng

Lo-Heng Chang

Ru-Gun Liu

Charles Chew-Yuen Young

Kam-Tou Sio

Pei-Yu Wang

Hui-Ting Yang

Hsin-Ping Chen

Kun-Ming Huang

Yu-Xuan Huang

Yung-Hsu Wu

Shun Li Chen

Wei-Chen Chu

Ming-Yi Lin

Meng-Huan Jao

Hsuan-Hui Hung

Kuo-Cheng Chiang

Hui-Zhong Zhuang

Zhi-Chang Lin

Guo-Huei Wu

Hsiang-Wei Liu

Kuan-lun Cheng

Lei-Chun Chou

Li-Lin Su

Yu-Chieh Liao

Chia-Lin Chuang

Tien-I Bao

Hai-Ching Chen

Shi Ning Ju

Sung-Li Wang

Hsin-Yen Huang

Yi-Hsiung Lin

Chi-Lin Teng

Wei-An Lai

Ting-Ya Lo

Chien Wen Lai

Hsiang-Lun Kao

Jian-Hua Chen

Ethan Hsiao

Wayne Lai

Jia-Chuan You

Shin-Yi Yang

Cheng-Ting Chung

Shuen-Shin Liang

Chia-Hung Chu

Yi-Bo Liao

Jin Cai

Po-Chin Chang

Lipen Yuan

Fu-Hsiung Yang

Chao-Wei Tseng

Tzu Pei Chen

Chiao-Hao Chang

Yuting Cheng

Yun-Ju Fan

A semiconductor structure is provided, and includes a first fin structure, a second fin structure, and a third fin structure over a substrate. The second fin structure is located between the first fin structure and the third fin structure. The semiconductor structure also includes a fin isolation structure formed between the first fin structure and the third fin structure; and a gate structure formed over the first fin structure, the second fin structure, the third fin structure and the fin isolation structure. The semiconductor structure further includes a plurality of epitaxial structures formed over the first fin structure, the second fin structure and the third fin structure. The semiconductor structure includes a dielectric material over the first epitaxial structure, the second epitaxial structure, and the third epitaxial structure; and a contact formed in the dielectric material and connected to the first epitaxial structure and the third epitaxial structure.

Semiconductor structure and method for forming the same

Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure.

Semiconductor device having backside via and method of fabricating thereof

A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.

Air spacer and capping structures in semiconductor devices

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first conductive structure disposed over the device, and the first conductive structure includes a first sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer disposed on the first portion, a second conductive structure disposed adjacent the first conductive structure, and the second conductive structure includes a second sidewall having a third portion and a fourth portion. The semiconductor device structure further includes a second spacer layer disposed on the third portion, and an air gap is formed between the first conductive structure and the second conductive structure. The second portion, the first spacer layer, the fourth portion, and the second spacer layer are exposed to the air gap.

Semiconductor device structure and methods of forming the same

A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

Method for forming long channel back-side power rail device

A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.

Semiconductor devices with backside power rail and method thereof

A device includes a substrate and a transistor on the substrate. The transistor includes a channel region that has at least one semiconductor nanostructure, and a gate electrode. A source/drain region is disposed adjacent to a first side of the channel region along a first direction. A hybrid fin structure is disposed adjacent to a second side of the channel region along a second direction that is transverse to the first direction. The hybrid fin structure includes a first hybrid fin dielectric layer and a second hybrid fin dielectric layer. The first and second hybrid fin dielectric layers include silicon, oxygen, carbon and nitrogen and have a different concentration of at least one of silicon oxygen, carbon, or nitrogen from one another.

Semiconductor device having dielectric hybrid fin

A semiconductor device structure includes a source/drain (S/D) feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a first silicide layer in contact with the first surface of the S/D feature, a second silicide layer opposing the first silicide layer and in contact with the second surface of the S/D feature, a front side S/D contact in contact with the first silicide layer, a back side S/D contact in contact with the second silicide layer, a semiconductor channel layer comprising a sidewall in contact with the sidewall of the source/drain feature, a gate dielectric layer surrounding exposed surfaces of the semiconductor layer, an interlayer dielectric (ILD) disposed adjacent to the gate dielectric layer, and a liner disposed between and in contact with the ILD and the gate dielectric layer.

Semiconductor device with backside power rail and methods of fabrication thereof

A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

Source/drain contacts and methods of forming same

A device includes a substrate. A channel region of a transistor overlies the substrate and a source/drain region is in contact with the channel region. The source/drain region is adjacent to the channel region along a first direction. A source/drain contact is disposed on the source/drain region. A gate electrode is disposed on the channel region and a gate contact is disposed on the gate electrode. A first low-k dielectric layer is disposed between the gate contact and the source/drain contact along the first direction.

Semiconductor device having a gate contact on a low-k liner

A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The semiconductor device structure includes a first source/drain (S/D) structure formed adjacent to the gate structure, and a first S/D contact structure formed over the first S/D structure. The semiconductor device structure includes a first filling layer formed over the first S/D structure, and the first S/D contact structure is surrounded by the first filling layer. The semiconductor device structure includes a dielectric layer formed adjacent to the gate structure and the first filling layer, and the dielectric layer and the first filling layer are made of different materials. The first filling layer is surrounded by the dielectric layer.

Semiconductor device structure and method for forming the same

A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

Connector via structures for nanostructures and methods of forming the same

A device includes a substrate and a gate structure wrapping around at least one vertical stack of nanostructure channels. The device includes a source/drain region abutting the gate structure, and a source/drain contact over the source/drain region. The device includes an etch stop layer laterally between the source/drain contact and the gate structure and having a first sidewall in contact with the source/drain contact, and a second sidewall opposite the first sidewall. The device includes a source/drain contact isolation structure embedded in the source/drain contact and having a third sidewall substantially coplanar with the second sidewall of the etch stop layer.

Field effect transistor with source/drain contact isolation structure and method

Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Backside gate contact

A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary method includes receiving a workpiece including a dielectric layer and a contact via extending through the dielectric layer, selectively forming a metal feature on a top surface of the contact via, forming a barrier layer over the metal feature and the dielectric layer, wherein the contact via is spaced apart from the barrier layer, and, forming a metal fill layer over the barrier layer. The metal feature is formed of a first material and the barrier layer is formed of a second material different from the first material.

Interconnect structure

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New Taipei, Taiwan

Cheng-Chi Chuang