Taiwan Semiconductor Manufacturing Comp. Ltd.

Chender Huang

Pei-Haw Tsao

Ken Hui Chen

Hank Huang

Jones Wang

Chao-Yuan Su

Chung Yu Wang

Chung-Yu Wang

Shin-Puu Jeng

Hao-Yi Tsai

Chenming Hu

Hsin-Hui Lee

Chuen-Jye Lin

Shang Y Hou

Allan Lin

Jeffrey Hsu

Chien-Hsiun Lee

Pei-Hwa Tsao

Shang-Yu Hou

Chia-Hsiung Hsu

Daniel Lee

Ken Chen

Pei Haw Tsao

A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip.

Fabrication method of package structure with simplified encapsulation structure and simplified wiring

Package structure and fabrication method thereof

A matrix form semiconductor package substrate that has an electrode situated in-between a plurality of IC package substrates for providing electrical communication to conductive pads on the substrate is provided. The matrix form semiconductor package substrate includes a plurality of IC package substrates that are integrally formed on a strip in a matrix pattern that has a boundary between each two of the plurality of IC package substrates. Each of the plurality of IC package substrates has a multiplicity of conductive pad traces and an electrode, or a plating bar, formed in a serpentine configuration along the boundary for providing electrical communication to the multiplicity of conductive pads.

Matrix form semiconductor package substrate having an electrode of serpentine shape

A new method is provided for the interface between a stress relieve interface layer of polyimide and a thereover created layer of mold compound. The invention provides for creating a pattern in the stress relieve layer of polyimide before the layer of mold compound is formed over the stress relieve layer of polyimide.

Enhanced adhesion strength between mold resin and polyimide

A heat spreader and package structure utilizing the same. The heat spreader is embedded in an encapsulant of a package and above a chip therein, wherein the package has a substrate, having a molding gate, and the chip has a center and a corner which is the farthest from the molding gate. The spreader includes a base with a hollow portion therethrough, a plurality of support leads, protruding from the base, on the inner edge, and a cap plate, having a hole at least directly above a region between the center and the corner of the chip, fixed by the support leads to be above the hollow portion, the cap plate.

Heat spreader and package structure utilizing the same

A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area Ais defined on the first scribe line and is defined by the equation A=D&#xd7;S, where Dis the distance from the corner point of the die toward the main area of the die, and Sis the width of the first scribe line. Free area Ais defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation A=S&#xd7;S, where Sis the width of the second scribe line.

Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling

Described is a semiconductor device having improved semiconductor bond pad reliability and methods of manufacturing thereof. The semiconductor device includes a layer formed over an integrated circuit on a semiconductor substrate. The first layer includes a conductive portion and an insulating portion. A second layer is then formed over the first layer and includes a conductive portion corresponding to the first layer's conductive portion and an insulating portion corresponding to the first layer's insulating portion. A bond pad is then formed over the first and second layers such that the bond pad is substantially situated above the conductive portions and the insulating portions of the first and second layers. A bonding ball is then formed on the bond pad substantially above the conduction portion of the first and second layers.

Semiconductor bond pad structures and methods of manufacturing thereof

A microelectronic package comprising a device substrate having first and second opposing surfaces and comprising a plurality of microelectronic devices. The microelectronic package also includes a plurality of electrically conductive members coupled to corresponding ones of the plurality of microelectronics device and extending away from the first surface. A thermally conductive layer is located on the second surface of the device substrate, and a package substrate is coupled to the device substrate, the package substrate having a plurality of electrically conductive traces coupled to corresponding ones of the plurality of electrically conductive members.

Thermal dispensing enhancement for high performance flip chip BGA (HPFCBGA)

A method of making a microelectronic assembly buying restraining a substrate in a fixture at room temperature, placing a flip chip on the substrate so that conductive bumps on the flip chip are aligned with contact pads on the substrate, heating the flip chip, the substrate and the fixture to reflow the conductive bumps on the flip chip, cooling the flip chip, substrate and fixture to solidify the conductive bumps and to mount the flip chip to the substrate, depositing an underfill between the flip chip and the substrate, curing the underfill by heating the flip chip, substrate, underfill and fixture to an elevated temperature, and removing the flip chip mounted substrate from the fixture.

Method for stress reduction in flip chip bump during flip chip mounting and underfill process steps of making a microelectronic assembly

A new method is provided for the interconnection of flip chips to a supporting substrate. The invention starts with a conventional first substrate, that serves as a semiconductor device support structure, over the surface of which a first pattern of contacts points has been provided. The invention then uses a second substrate, for instance a glass or quartz plate, and creates over the surface thereof a second pattern of solder bumps separated by solder non-wettable surfaces. The second pattern is a mirror image of the first pattern. By then overlying the first pattern of contact points with the second pattern of solder bumps, a step of reflow can be applied to the solder bumps, transferring the solder bumps from the second substrate to the contact points provided over the first substrate.

Buildup substrate pad pre-solder bump manufacturing

The invention includes a method of wafer level chip scale packaging including providing a semiconductor device having a silicon based substrate with discrete devices defined therein and a contact pad near an upper surface thereof, a passivation layer overlying the silicon based substrate and the contact pad, and the passivation layer having an opening therein exposing at least a portion of the contact pad, and a redistribution trace electrically connected to the contact pad near a first end and having a second end of spaced a distance from the contact pad. Forming an encapsulation layer over the semiconductor device including the redistribution trace. Forming an opening in the encapsulation layer down to the redistribution trace. Forming a contact post in the opening in the encapsulation layer, and the contact post having a first end electrically connected to the redistribution trace and a second exposed end. Forming an electrically conductive bump on the semiconductor device and in electrical contact with the contact post.

Method of wafer level chip scale packaging

A method for protecting a passivation layer during a solder bump formation process including providing a semiconductor process wafer having a process surface including at least two metal layers comprising an uppermost metal layer and a lowermost metal layer said lowermost metal layer overlying a passivation layer including metal bonding pad regions; photolithographically patterning and anisotropically etching through a first thickness portion of at least the uppermost metal layer to form a first patterned metal layer portion disposed over the metal bonding pad regions and reveal a second thickness portion including the lowermost metal layer; forming a solder bump over the first patterned metal layer portion according to at least a first reflow process; and, anisotropically etching through the second thickness portion surrounding the completely formed solder bump to reveal the passivation layer.

Growing community of inventors

Hsin-Chu, Taiwan

Chender Huang