Marvell International Limited

Chender Chen

Chenglin Liu

Shiann-Ming Liou

Xiaoting Chang

A packaged IC having laser vias and methods for making the same. The packaged IC includes a die having bond pads thereon, wire bonds contacting the bond pads, and a substrate configured to electrically connect the wire bonds and external package connectors. The substrate includes mechanical vias through the substrate layers and laser vias in an uppermost substrate layer. Each laser via is closer to the die than the mechanical vias that do not overlap or are not covered by the die. The method includes routing traces on uppermost and lowermost layers, the traces electrically connecting a wire bonds and external package connectors, forming mechanical vias through all layers of the substrate, forming laser vias in the uppermost substrate layer, and electrically connecting each wire bond to one trace on the uppermost substrate layer.

Ball grid array package with laser vias and methods for making the same

In one embodiment, the present invention includes a lead frame for accommodating a semiconductor die. The lead frame includes a die attach pad, a first plurality of conductive finger ends, and a second plurality of conductive finger ends. The first plurality of conductive finger ends are arranged within a first elongated region. This first elongated region is located along the first edge of the die attach pad. The second plurality of conductive finger ends is arranged within a second elongated region. The second elongated region has an end adjacent to an end of the first elongated region. The second elongated region is positioned at an angle that is greater than ninety degrees from the first elongated region.

Lead frame apparatus and method for improved wire bonding

A packaged IC having laser vias and methods for making the same. The packaged IC includes a die having bond pads thereon, wire bonds contacting the bond pads, and a substrate configured to electrically connect the wire bonds and external package connectors. The substrate includes mechanical vias through the substrate layers and laser vias in an uppermost substrate layer. Each laser via is closer to the die than the mechanical vias that do not overlap or are not covered by the die. The method includes routing traces on uppermost and lowermost layers, the traces electrically connecting wire bonds and external package connectors, forming mechanical vias through all layers of the substrate, forming laser vias in the uppermost substrate layer, and electrically connecting each wire bond to one trace on the uppermost substrate layer.

Embodiments of the present disclosure provide an apparatus comprising a substrate layer, a metal ring structure disposed on the substrate layer, the metal ring structure having an opening defined therein, and a solder mask layer coupled to (i) the metal ring structure and (ii) the substrate layer through the opening defined in the metal ring structure, the solder mask layer having a solder mask opening defined therein, wherein an edge of solder mask material defining the solder mask opening overlaps a portion of the opening defined in the metal ring structure. Other embodiments may be described and/or claimed.

Metal ring techniques and configurations

Embodiments of the present disclosure describe semiconductor device packaging techniques and devices that incorporate a heat spreader into the insulating material of a packaged semiconductor device. In one embodiment, a device comprising a semiconductor device is coupled to a substrate, and insulating material covers (i) a portion of the semiconductor device and (ii) a portion of the substrate. The device also comprises a heat spreader embedded in the insulating material and the heat spreader is isolated from the substrate at least in part by the insulating material.

Placing heat sink into packaging by strip formation assembly

Method and apparatuses directed to printed circuit boards (PCB) including plated through-holes for interconnecting to plating busses are described herein. A PCB strip may include an inner circuitry layer comprising a plurality of trace lines, and a top circuitry layer formed over the inner circuitry layer, the top circuitry layer including a plating bus, and at least one plated through-hole interconnecting the plating bus to one or more trace lines of the inner circuitry layer. The plating bus of the top circuitry layer and the plated through-holes may be located within at least one saw street of the PCB strip.

Growing community of inventors

Fongyuan, Taiwan

Chender Chen