Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Yu Tsai

Wen-Chih Chiou

Shin-Puu Jeng

Ku-Feng Yang

Chen-Hua Douglas Yu

Fang Wen Tsai

Tsang-Jiuh Wu

Jing-Cheng Lin

Weng-Jin Wu

Hsin-Yu Chen

Yu-Sheng Lin

Ming-Tsu Chung

Chia-Ho Chen

Hong-Ye Shih

Shih-Hui Wang

Jiung Wu

Chien-Ming Chiu

Tsung-Shang Wei

A semiconductor apparatus for pre-wetting a semiconductor workpiece includes a process chamber, a workpiece holder disposed within the process chamber to hold the semiconductor workpiece, a pre-wetting fluid tank disposed outside the process chamber and containing a pre-wetting fluid, and a conduit coupled to the pre-wetting fluid tank and extending into the process chamber. The conduit delivers the pre-wetting fluid from the pre-wetting fluid tank out through an outlet of the conduit to wet a major surface of the semiconductor workpiece, wherein the outlet of the conduit is positioned above the major surface of the semiconductor workpiece by a vertical distance.

Apparatus and method for wafer pre-wetting

A semiconductor structure including a first die, a second die stacked on the first die, a smoothing layer disposed on the first die and a filling material layer disposed on the smoothing layer. The second die has a dielectric portion and a semiconductor material portion disposed on the dielectric portion. The smoothing layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is disposed on the first dielectric layer. The dielectric portion is surrounded by the smoothing layer, and the semiconductor material portion is surrounded by the filling material layer. A material of the first dielectric layer is different from a material of the second dielectric layer and a material of the filling material layer.

Semiconductor structure and manufacturing method thereof

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an interconnect structure disposed over a semiconductor substrate, contact pads disposed on the interconnect structure, a dielectric structure disposed on the interconnect structure and covering the contact pads, bonding connectors covered by the dielectric structure and landing on the contact pads, and a dummy feature covered by the dielectric structure and laterally interposed between adjacent two of the bonding connectors. Top surfaces of the bonding connectors are substantially coplanar with a top surface of the dielectric structure, and the bonding connectors are electrically coupled to the interconnect structure through the contact pads.

Semiconductor structure comprising dummy feature interposed between the bonding connectors

A plating apparatus includes a workpiece holder, a plating bath, and a clamp ring. The plating bath is underneath the workpiece holder. The clamp ring is connected to the workpiece holder. The clamp ring includes channels communicating an inner surface of the clamp ring and an outer surface of the clamp ring.

Plating apparatus for plating semiconductor wafer and plating method

A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

Bonding structures of integrated circuit devices and method forming the same

A semiconductor apparatus and methods of processing a semiconductor workpiece are provided. The semiconductor apparatus for pre-wetting a semiconductor workpiece includes a process chamber, a workpiece holder disposed within the process chamber to hold the semiconductor workpiece, a pre-wetting fluid tank disposed outside the process chamber and containing a pre-wetting fluid, and a conduit coupled to the pre-wetting fluid tank and extending into the process chamber. The conduit delivers the pre-wetting fluid from the pre-wetting fluid tank out through an outlet of the conduit to wet a major surface of the semiconductor workpiece comprising a plurality of recess portions.

A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.

Method of making semiconductor device package including conformal metal cap contacting each semiconductor die

In accordance with an embodiment a method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.

Semiconductor device package including conformal metal cap contacting each semiconductor die

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.

Self-alignment for redistribution layer

A device includes a through substrate via (TSV) extending through a device substrate. The TSV includes a first conductive material having a sidewall, a protruding end of the TSV protruding from a second side of the device substrate. A liner covers the sidewall of the first conductive material from a below the top surface of the protruding end of the TSV to an opposite end of the TSV. A passivation layer is disposed over the second side of the device substrate and over a portion of the liner disposed on the protruding end of the TSV, the passivation layer having a stair-step surface extending away from the TSV. A conductive interface layer is disposed over the passivation layer, the sidewall of the first conductive material, and the top surface of the protruding end of the TSV. A second conductive material is disposed over the first conductive material.

Through silicon via structure

A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.

Method for through silicon via structure

In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

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Zhongli, Taiwan

Chen-Yu Tsai