Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Nan Yeh

Chen-Hua Douglas Yu

Cheng-Hung Chang

Yu-Rung Hsu

Chu-Yun Fu

Ding-Yuan Chen

Chen-Yi Lee

Shih-Ting Hung

Cheng-Tung Lin

Chin-Hsiang Lin

Chao-Cheng Chen

Hun-Jan Tao

Tsung-Lin Lee

Chih-Hao Chang

Sey-Ping Sun

Jye-Yen Cheng

Chih-Hsiang Yao

Wen-Kai Wan

Hsiang-Yi Wang

Chao-An Jong

Yung-Cheng Lu

Ryan Chia-Jen Chen

Li-Te S Lin

Jyu-Horng Shieh

Tsang-Jiuh Wu

Liang-Gi Yao

Yi-Nien Su

Yuan-Hung Chiu

Tsiao-Chen Wu

Li-Chih Chao

Mong Song Liang

Jang-Shiang Tsai

Miao-Ju Hsu

Chien-Chung Fu

Yu-Rang Hsu

A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

FinFETs having dielectric punch-through stoppers

System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

System and method for source/drain contact processing

A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.

Method of fabricating semiconductor device isolation structure

A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

Dielectric punch-through stoppers for forming FinFETs having dual Fin heights

A semiconductor device includes a gate stack overlying a substrate. The semiconductor device further includes a spacer on sidewalls of the gate stack, where a top surface of the spacer is above a top surface of the gate stack. Additionally, the semiconductor device includes a protection layer overlying the gate stack and filling at least a portion of a space surrounded by the spacer above the top surface of the gate stack. Furthermore, the semiconductor device includes a contact hole over the spacer, where the contact hole extends over the gate stack, and where a sidewall of the contact hole has a step-wise shape.

Semiconductor device having elevated structure

A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.

Reducing resistance in source and drain regions of FinFETs

Dielectric punch-through stoppers for forming FinFETs having dual fin heights

A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

Germanium FinFETs having dielectric punch-through stoppers

A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack.

Semiconductor device having elevated structure and method of manufacturing the same

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Hsi-Chih, Taiwan

Chen-Nan Yeh