Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Jong Wang

Mong-Song Liang

Shou-Gwo Wuu

Chia-Shiung Tsai

Xiaomeng Chen

Kuo-Chyuan Tzeng

Chung-Hui Su

Kuo-Chi Tu

Dun-Nian Yaung

Shih-Chang Liu

Jhy-Jyi Sze

Chern-Yow Hsu

Yimin Huang

Wen-Chuan Chiang

Hsiang-Fan Lee

Wei Chuang Wu

Jen-Cheng Liu

Seiji Takahashi

Feng-Chi Hung

Ping-Yin Liu

Lan-Lin Chao

Xin-Hua Huang

Wei-Cheng Hsu

Alexander Kalnitsky

Ching-Chun Wang

Chun-Wei Chang

Chien-Hsien Tseng

Feng-Jia Shiu

Dennis Sinitsky

Chung-Wei Chang

Luan Conn Tran

Jung-I Lin

Yu-Jen Wang

Yuichiro Yamashita

Szu-Ying Chen

Ming Chyi Liu

Tzu-Hsuan Hsu

Shyh-Fann Ting

Keng-Yu Chou

Bruce C S Chou

Jenn Ming Huang

Tzu-Jui Wang

Wei-Chieh Chiang

Kazuaki Hashimoto

Jung-Kuo Tu

Tse-Liang Ying

Chun-Yao Chen

Chun-Ming Su

Wen-Cheng Chen

Tsung-Te Chou

Jin-Yuan Lee

Yeur-Luen Tu

Tien-Lu Lin

Hsun-Chung Kuang

Tai-I Yang

Kuo-Ji Chen

Kuo-Ching Huang

Ming-Hsiang Song

Chien-Hua Huang

Ta-Chun Lin

Chih-Hui Huang

Chue-San Yoo

Min-Hsiung Chiang

Kun-Lung Chen

Chin-Chia Kuo

Chung S Wang

Tung-Ting Wu

Julie Huang

Ming-Chieh Hsu

Huey-Chi Chu

Yi-Ching Lin

Kevin Chiang

Ping Yang

Yi-Shin Chu

Kuan-Chieh Huang

Yuan-Chang Huang

Wen-I Hsu

Shang-Fu Yeh

Chue San Yoo

Kuo Ching Huang

Chih-Yang Pai

Kuo-Hsien Cheng

Yung-Kuan Hsiao

Hung-Chang Chien

Shen-Hui Hong

Chen-Yong Lin

Chi-Hsien Chung

Xin-Chung Kuang

Chi-Hsing Lo

Min-Hsiang Chiang

King Liao

Wen-Chaun Chiang

Chung Hsin Fang

Shih-Min Huang

Chia-Chiung Tsai

In some embodiments, the present disclosure relates to a single-photon avalanche detector (SPAD) device including a silicon substrate including a recess in an upper surface of the silicon substrate. A p-type region is arranged in the silicon substrate below a lower surface of the recess. An n-type avalanche region is arranged in the silicon substrate below the p-type region and meets the p-type region at a p-n junction. A germanium region is disposed within the recess over the p-n junction.

Semiconductor device including germanium region disposed in semiconductor substrate

Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first chip bonded to a second chip. The first chip includes a semiconductor substrate. The first chip includes a first transistor cell and a second transistor cell. The second transistor cell is laterally spaced from the first transistor cell. A first through-substrate via (TSV) extends vertically through the semiconductor substrate. The first transistor cell is electrically coupled to the first TSV. A second TSV extends vertically through the first semiconductor substrate. The second transistor cell is electrically coupled to the second TSV. The second chip comprises a first readout circuit that is electrically coupled to the first TSV and the second TSV. The first readout circuit is disposed laterally between the first TSV and the second TSV. The first readout circuit is configured to receive a first signal from the first transistor cell.

High-speed readout image sensor

Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a deep trench isolation (DTI) structure disposed in a substrate. A pixel region of the substrate is disposed within an inner perimeter of the DTI structure. A photodetector is disposed in the pixel region of the substrate. A gate electrode structure overlies, at least partially, the pixel region of the substrate. A first gate dielectric structure partially overlies the pixel region of the substrate. A second gate dielectric structure partially overlies the pixel region of the substrate. The gate electrode structure overlies both a portion of the first gate dielectric structure and a portion of the second gate dielectric structure. The first gate dielectric structure has a first thickness. The second gate dielectric structure has a second thickness that is greater than the first thickness.

Image sensor having a gate dielectric structure for improved device scaling

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor device, the method including forming a plurality of photodetectors in a substrate. A device isolation structure is formed within the substrate. The device isolation structure laterally wraps around the plurality of photodetectors. An outer isolation structure is formed within the substrate. The device isolation structure is spaced between sidewalls of the outer isolation structure. The device isolation structure and the outer isolation structure comprise a dielectric material.

Device crack-stop structure to prevent damage due to dicing crack

In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.

Semiconductor imaging device having improved dark current performance

A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.

Semiconductor arrangement with capacitor

A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a plurality of pixel sensors, an isolation grid disposed in the substrate and separating the plurality of pixel sensors from each other, a reflective grid disposed over the isolation grid on the back side of the substrate, an a low-n grid disposed over the back side of the substrate and overlapping the reflective grid from a top view. A width of the low-n grid is greater than a width of the reflective grid.

Semiconductor image sensor

In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.

Various embodiments of the present disclosure are directed towards a semiconductor structure including a crack-stop structure disposed within a semiconductor substrate. The semiconductor substrate has a back-side surface and a front-side surface opposite the back-side surface. Photodetectors are disposed within the semiconductor substrate and are laterally spaced within a device region. An interconnect structure is disposed along the front-side surface. The interconnect structure includes a seal ring structure. A crack-stop structure is disposed within the semiconductor substrate and overlies the seal ring structure. The crack-stop structure continuously extends around the device region.

The present disclosure relates to a CMOS image sensor having a doped isolation structure separating a photodiode and a pixel device, and an associated method of formation. In some embodiments, the CMOS image sensor has a doped isolation structure separating a photodiode and a pixel device. The photodiode is arranged within the substrate away from a front-side of the substrate. A pixel device is disposed at the front-side of the substrate overlying the photodiode and is separated from the photodiode by the doped isolation structure. Comparing to previous image sensor designs, where an upper portion of the photodiode is commonly arranged at a top surface of a front-side of the substrate, now the photodiode is arranged away from the top surface and leaves more room for pixel devices. Thus, a larger pixel device can be arranged in the sensing pixel, and short channel effect and noise level can be improved.

High density image sensor

A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.

Semiconductor arrangement with capacitor and method of fabricating the same

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric structure disposed over a substrate. A plurality of conductive interconnect layers are disposed within the dielectric structure. The plurality of conductive interconnect layers include alternating layers of interconnect wires and interconnect vias. A metal-insulating-metal (MIM) capacitor is arranged within the dielectric structure. The MIM capacitor has a lower conductive electrode separated from an upper conductive electrode by a capacitor dielectric structure. The MIM capacitor vertically extends past two or more of the plurality of conductive interconnect layers.

High density MIM capacitor structure

An image sensor is disclosed. The image sensor includes an epitaxial layer, a plurality of plug structures and an interconnect structure. Wherein the plurality of plug structures are formed in the epitaxial layer, and each plug structure has doped sidewalls, the epitaxial layer and the doped sidewalk form a plurality of photodiodes, the plurality of plug structures are used to separate adjacent photodiodes, and the epitaxial layer and the doped sidewalls are coupled to the interconnect structure via the plug structures. An associated method of fabricating the image sensor is also disclosed. The method includes: providing a substrate having a first-type doped epitaxial substrate layer on a second-type doped epitaxial substrate layer; forming a plurality of isolation trenches in the first-type doped epitaxial substrate layer; forming a second-type doped region along sidewalk and bottoms of the plurality of isolation trenches; and filling the plurality of isolation trenches by depositing metal.

Implant damage free image sensor and method of the same

A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.

Semiconductor arrangement having capacitor separated from active region

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Hsin-Chu, Taiwan

Chen-Jong Wang