Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Solid State Lighting Ltd.

Taiwan Union Technology Corporation

Epistar Corporation

Parabellum Strategic Opportunities Fund LLC

Other

Imec

Chen-Hua Douglas Yu

Chung-Shi Liu

Hao-Yi Tsai

Wen-Chih Chiou

Hsien-Wei Chen

Chuei-Tang Wang

Der-Chyang Yeh

Jing-Cheng Lin

Shin-Puu Jeng

Kuo-Chung Yee

Ming-Fa Chen

Chi-Hsi Wu

Hung-Jui Kuo

Mirng-Ji Lii

Jiun Yi Wu

Shang-Yun Hou

An-Jhih Su

Tin-Hao Kuo

Ming-Da Cheng

Syun-Ming Jang Jang

Chung-Hao Tsai

Wei-Cheng Wu

Hung-Yi Kuo

Sung-Feng Yeh

Chien-Hsun Lee

Chih-Wei Lin

Jui-Pin Hung

Weng-Jin Wu

Szu-Wei Lu

Cheng-Chieh Hsieh

Yu-Hsiang Hu

Chien Ling Hwang

Shau-Lin Shue

Kai-Chiang Wu

Tsang-Jiuh Wu

Po-Hao Tsai

Tien-I Bao

Ying-Ching Shih

Ching-Hua Hsieh

Yu-Feng Chen

Wei-Yu Chen

Tsung-Yuan Yu

Chen-Shien Chen

Chao-Wen Shih

Chih-Hua Chen

Wei-Hung Lin

Li-Hsien Huang

Meng-Tse Chen

Wei-Ting Chen

Tsung-Ding Wang

Tsung-Shu Lin

Ying-Ju Chen

Hsiu-Jen Lin

Tzuan-Horng Liu

Jie Chen

Hai-Ching Chen

Han-Ping Pu

Yen-Liang Lin

Ming-Che Ho

Chih-Wei Wu

Cheng-Lin Huang

Chewn-Pu Jou

Ching-Wen Hsiao

Horng-Huei Tseng

Wen-Shiang Liao

Keng-Chu Lin

Yung-Cheng Lu

Wen-Hsiung Lu

Feng Wei Kuo

Ming-Hsing Tsai

Alexander Kalnitsky

Mei-Yun Wang

Yi-Wen Wu

Mong-Song Liang

Chung-Chi Ko

Chen-Cheng Kuo

Yun-Han Lee

Chia-Shiung Tsai

Chao-Cheng Chen

Chenming Hu

Jeng-Horng Chen

Shy-Jay Lin

Burn Jeng Lin

Chun-Hung Lin

Shih-Chang Chen

Yih Wang

Anthony Yen

Shuo-Mao Chen

Chih-Hao Chang

Li-Hui Cheng

Weng Chang

Tze-Liang Lee

Jin-Yuan Lee

Ying-Lang Wang

Hun-Jan Tao

Chao-Hsiung Wang

Ming Chyi Liu

Ming-Chih Yew

Hsueh-Chang Sung

Pei-Ren Jeng

A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.

Buffer design for package integration

In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

Integrated circuit package and method

In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.

An embodiment is a package including a package substrate and a package component bonded to the package substrate, the package component including an interposer, an optical die bonded to the interposer, the optical die including an optical coupler, an integrated circuit die bonded to the interposer adjacent the optical die, a lens adapter adhered to the optical die with a first optical glue, a mirror adhered to the lens adapter with a second optical glue, the mirror being aligned with the optical coupler of the optical die, and an optical fiber on the lens adapter, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical glue, the lens adapter, and the first optical glue to the optical coupler of the optical die.

Integrated circuit package and method of forming same

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Polymer layers embedded with metal pads for heat dissipation

A method includes forming a redistribution structure on a carrier substrate, coupling a first side of a first interconnect structure to a first side of the redistribution structure using first conductive connectors, where the first interconnect structure includes a core substrate, where the first interconnect structure includes second conductive connectors on a second side of the first interconnect structure opposite the first side of the first interconnect structure, coupling a first semiconductor device to the second side of the first interconnect structure using the second conductive connectors, removing the carrier substrate, and coupling a second semiconductor device to a second side of the redistribution structure using third conductive connectors, where the second side of the redistribution structure is opposite the first side of the redistribution structure.

Semiconductor device package and methods of manufacture

A die stacking structure, a semiconductor package and a method for forming the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; and a stack of dielectric layers, extending in between the second device dies, and laterally enclosing each of the second device dies. The dielectric layers are respectively formed of a spin-on-glass (SOG) or a polymer, and a lower one of the dielectric layers has a thickness greater than a thickness of another one of the dielectric layers at a higher level.

Die stacking structure, semiconductor package and formation method of the die stacking structure

A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

Fingerprint sensor device and method

A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. The plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package.

Packages with metal line crack prevention design

In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

Semiconductor package and method

A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

Semiconductor package system and method

Semiconductor devices and methods of forming the semiconductor devices are described herein. A method includes providing a first material layer between a second material layer and a semiconductor substrate and forming a first waveguide in the second material layer. The method also includes forming a photonic die over the first waveguide and forming a first cavity in the semiconductor substrate and exposing the first layer. Once formed, the first cavity is filled with a first backfill material adjacent the first layer. The methods also include electrically coupling an electronic die to the photonic die. Some methods include packaging the semiconductor device in a packaged assembly.

Structure and process for photonic packages

A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias.

Integrated fan-out packages and methods of forming the same

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.

Semiconductor structure having a conductive feature comprising an adhesion layer and a metal region over and contacting the adhesion layer

In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

Wafer bonding method

Growing community of inventors

Hsin-Chu, Taiwan

Chen-Hua Douglas Yu