Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Solid State Lighting Ltd.

Taiwan Union Technology Corporation

Epistar Corporation

Parabellum Strategic Opportunities Fund LLC

Other

Imec

Chen-Hua Douglas Yu

Chung-Shi Liu

Hao-Yi Tsai

Wen-Chih Chiou

Hsien-Wei Chen

Chuei-Tang Wang

Der-Chyang Yeh

Jing-Cheng Lin

Shin-Puu Jeng

Kuo-Chung Yee

Ming-Fa Chen

Chi-Hsi Wu

Hung-Jui Kuo

Mirng-Ji Lii

Jiun Yi Wu

Shang-Yun Hou

An-Jhih Su

Tin-Hao Kuo

Ming-Da Cheng

Syun-Ming Jang Jang

Chung-Hao Tsai

Wei-Cheng Wu

Hung-Yi Kuo

Sung-Feng Yeh

Chien-Hsun Lee

Chih-Wei Lin

Jui-Pin Hung

Weng-Jin Wu

Szu-Wei Lu

Yu-Hsiang Hu

Cheng-Chieh Hsieh

Chien Ling Hwang

Shau-Lin Shue

Kai-Chiang Wu

Tsang-Jiuh Wu

Po-Hao Tsai

Ying-Ching Shih

Tien-I Bao

Ching-Hua Hsieh

Yu-Feng Chen

Wei-Yu Chen

Chao-Wen Shih

Tsung-Yuan Yu

Chen-Shien Chen

Chih-Hua Chen

Wei-Hung Lin

Li-Hsien Huang

Meng-Tse Chen

Wei-Ting Chen

Tsung-Ding Wang

Tsung-Shu Lin

Ying-Ju Chen

Hsiu-Jen Lin

Tzuan-Horng Liu

Jie Chen

Han-Ping Pu

Hai-Ching Chen

Yen-Liang Lin

Ming-Che Ho

Chih-Wei Wu

Cheng-Lin Huang

Chewn-Pu Jou

Ching-Wen Hsiao

Horng-Huei Tseng

Wen-Shiang Liao

Keng-Chu Lin

Yung-Cheng Lu

Wen-Hsiung Lu

Ming-Hsing Tsai

Feng Wei Kuo

Alexander Kalnitsky

Mei-Yun Wang

Mong-Song Liang

Chung-Chi Ko

Chen-Cheng Kuo

Yun-Han Lee

Chia-Shiung Tsai

Chao-Cheng Chen

Chenming Hu

Jeng-Horng Chen

Shy-Jay Lin

Burn Jeng Lin

Chun-Hung Lin

Shih-Chang Chen

Yih Wang

Anthony Yen

Shuo-Mao Chen

Chih-Hao Chang

Li-Hui Cheng

Weng Chang

Fong-yuan Chang

Tze-Liang Lee

Jin-Yuan Lee

Ying-Lang Wang

Hun-Jan Tao

Chao-Hsiung Wang

Ming Chyi Liu

Ming-Chih Yew

Hsueh-Chang Sung

Pei-Ren Jeng

A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

Conductive traces in semiconductor devices and methods of forming same

A method of forming a semiconductor device includes attaching a first local interconnect component to a first substrate with a first adhesive, forming a first redistribution structure over a first side of the first local interconnect component, and removing the first local interconnect component and the first redistribution structure from the first substrate and attaching the first redistribution structure to a second substrate. The method further includes removing the first adhesive from the first local interconnect component and forming an interconnect structure over a second side of the first local interconnect component and the first encapsulant, the second side being opposite the first side. A first conductive feature of the interconnect structure is physically and electrically coupled to a second conductive feature of the first local interconnect component.

Semiconductor package and method of forming thereof

A package includes silicon waveguides on a first side of an oxide layer; photonic devices on the first side of the oxide layer, wherein the photonic devices are coupled to the silicon waveguides; redistribution structures over the first side of the oxide layer, wherein the redistribution structures are electrically connected to the photonic devices; a hybrid interconnect structure on a second side of the oxide layer, wherein the hybrid interconnect structure includes a stack of silicon nitride waveguides that are separated by dielectric layers; and through vias extending through the hybrid interconnect structure and the oxide layer, wherein the through vias make physical and electrical connection to the redistribution structures.

Photonic package and method of manufacture

A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.

Semiconductor device

A chip package structure is provided. The chip package structure includes a first redistribution layer having a bonding portion. The bonding portion includes a dielectric layer. The chip package structure includes a chip structure bonded to the bonding portion. A first width of the dielectric layer of the bonding portion is substantially equal to a second width of the chip structure. The chip package structure includes a protective layer over the first redistribution layer and surrounding the chip structure. A portion of the protective layer extends into the first redistribution layer and surrounds the bonding portion.

Chip package structure with redistribution layer having bonding portion

An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least laterally encapsulating the first die and the through via with an encapsulant, and forming a first redistribution structure over the first die, the through via, and the encapsulant. The forming the first redistribution structure including forming a first via on the through via, and forming a first metallization pattern on the first via, at least one sidewall of the first metallization pattern directly overlying the through via.

Package structures and method of forming the same

A package structure includes a first thermal dissipation structure. The first thermal dissipation structure includes a semiconductor substrate, conductive vias, a thermal transmission structure, first capacitors, bonding pads, and bonding vias. The conductive vias are embedded in the semiconductor substrate. The thermal transmission structure is disposed over the semiconductor substrate and the conductive vias. The thermal transmission structure includes a conductive plane. The first capacitors are at least partially embedded in the thermal transmission structure. The bonding pads and the bonding vias are embedded in the thermal transmission structure. The bonding vias electrically connect the conductive vias and the bonding pads. The conductive plane is in physical contact with sidewalls of at least one of the bonding pads.

Structure having thermal dissipation structure therein and manufacturing method thereof

In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

Integrated circuit package and method

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

Semiconductor device having underfill surrounding bottom package and solder ball

A method includes bonding a photonic engine onto an interposer, and bonding a package component onto the interposer. The package component includes a device die. The method further includes encapsulating the package component and the photonic engine in an encapsulant, attaching a thermal-electronic cooler to the photonic engine, and attaching a metal lid to the package component.

Thermo-electric cooler for dissipating heat of optical engine

An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.

3D integrated circuit (3DIC) structure

An apparatus and a method for effectively exhausting evaporated material are provided. In an embodiment the apparatus includes a hot plate and an exhaust hood assembly suspended over the hot plate. The exhaust hood assembly includes a trench plate, a cover plate over the trench plate and a single exhaust pipe header over and attached to a single exhaust opening of the cover plate. During operation, the exhaust hood assembly reduces the amount of condensation and also collects any remaining condensation in order to help prevent condensation from impacting further manufacturing steps.

Apparatus, system and method

A chip stack structure is provided. The chip stack structure includes a first chip including a first substrate and a first interconnect structure over the first substrate. The chip stack structure includes a second chip over and bonded to the first chip. The second chip has a second interconnect structure and a second substrate over the second interconnect structure. The chip stack structure includes an insulating layer over the second interconnect structure and surrounding the second substrate. The chip stack structure includes a conductive plug penetrating through the insulating layer to the second interconnect structure.

Chip stack structure with conductive plug and method for forming the same

A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.

Buffer design for package integration

In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

Growing community of inventors

Hsin-Chu, Taiwan

Chen-Hua Douglas Yu