Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Solid State Lighting Ltd.

Taiwan Union Technology Corporation

Epistar Corporation

Parabellum Strategic Opportunities Fund LLC

Other

Imec

Chen-Hua Douglas Yu

Chung-Shi Liu

Hao-Yi Tsai

Wen-Chih Chiou

Chuei-Tang Wang

Hsien-Wei Chen

Der-Chyang Yeh

Jing-Cheng Lin

Shin-Puu Jeng

Kuo-Chung Yee

Ming-Fa Chen

Chi-Hsi Wu

Hung-Jui Kuo

Mirng-Ji Lii

Jiun Yi Wu

Shang-Yun Hou

An-Jhih Su

Tin-Hao Kuo

Ming-Da Cheng

Syun-Ming Jang Jang

Chung-Hao Tsai

Wei-Cheng Wu

Hung-Yi Kuo

Sung-Feng Yeh

Chien-Hsun Lee

Chih-Wei Lin

Jui-Pin Hung

Weng-Jin Wu

Szu-Wei Lu

Yu-Hsiang Hu

Cheng-Chieh Hsieh

Chien Ling Hwang

Shau-Lin Shue

Kai-Chiang Wu

Tsang-Jiuh Wu

Po-Hao Tsai

Ying-Ching Shih

Tien-I Bao

Ching-Hua Hsieh

Yu-Feng Chen

Wei-Yu Chen

Tsung-Yuan Yu

Chen-Shien Chen

Chao-Wen Shih

Chih-Hua Chen

Wei-Hung Lin

Li-Hsien Huang

Meng-Tse Chen

Wei-Ting Chen

Tsung-Ding Wang

Tsung-Shu Lin

Ying-Ju Chen

Hsiu-Jen Lin

Tzuan-Horng Liu

Jie Chen

Hai-Ching Chen

Han-Ping Pu

Yen-Liang Lin

Ming-Che Ho

Chih-Wei Wu

Cheng-Lin Huang

Chewn-Pu Jou

Ching-Wen Hsiao

Horng-Huei Tseng

Wen-Shiang Liao

Keng-Chu Lin

Yung-Cheng Lu

Wen-Hsiung Lu

Feng Wei Kuo

Ming-Hsing Tsai

Alexander Kalnitsky

Mei-Yun Wang

Yi-Wen Wu

Mong-Song Liang

Chung-Chi Ko

Chen-Cheng Kuo

Yun-Han Lee

Chia-Shiung Tsai

Chao-Cheng Chen

Chenming Hu

Jeng-Horng Chen

Shy-Jay Lin

Burn Jeng Lin

Chun-Hung Lin

Shih-Chang Chen

Yih Wang

Anthony Yen

Shuo-Mao Chen

Chih-Hao Chang

Li-Hui Cheng

Weng Chang

Tze-Liang Lee

Jin-Yuan Lee

Ying-Lang Wang

Hun-Jan Tao

Chao-Hsiung Wang

Ming Chyi Liu

Ming-Chih Yew

Hsueh-Chang Sung

Pei-Ren Jeng

A package structure includes a first thermal dissipation structure. The first thermal dissipation structure includes a semiconductor substrate, conductive vias, a thermal transmission structure, first capacitors, bonding pads, and bonding vias. The conductive vias are embedded in the semiconductor substrate. The thermal transmission structure is disposed over the semiconductor substrate and the conductive vias. The thermal transmission structure includes a conductive plane. The first capacitors are at least partially embedded in the thermal transmission structure. The bonding pads and the bonding vias are embedded in the thermal transmission structure. The bonding vias electrically connect the conductive vias and the bonding pads. The conductive plane is in physical contact with sidewalls of at least one of the bonding pads.

Structure having thermal dissipation structure therein and manufacturing method thereof

In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

Integrated circuit package and method

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

Semiconductor device having underfill surrounding bottom package and solder ball

A method includes bonding a photonic engine onto an interposer, and bonding a package component onto the interposer. The package component includes a device die. The method further includes encapsulating the package component and the photonic engine in an encapsulant, attaching a thermal-electronic cooler to the photonic engine, and attaching a metal lid to the package component.

Thermo-electric cooler for dissipating heat of optical engine

An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.

3D integrated circuit (3DIC) structure

An apparatus and a method for effectively exhausting evaporated material are provided. In an embodiment the apparatus includes a hot plate and an exhaust hood assembly suspended over the hot plate. The exhaust hood assembly includes a trench plate, a cover plate over the trench plate and a single exhaust pipe header over and attached to a single exhaust opening of the cover plate. During operation, the exhaust hood assembly reduces the amount of condensation and also collects any remaining condensation in order to help prevent condensation from impacting further manufacturing steps.

Apparatus, system and method

A chip stack structure is provided. The chip stack structure includes a first chip including a first substrate and a first interconnect structure over the first substrate. The chip stack structure includes a second chip over and bonded to the first chip. The second chip has a second interconnect structure and a second substrate over the second interconnect structure. The chip stack structure includes an insulating layer over the second interconnect structure and surrounding the second substrate. The chip stack structure includes a conductive plug penetrating through the insulating layer to the second interconnect structure.

Chip stack structure with conductive plug and method for forming the same

A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.

Buffer design for package integration

In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.

An embodiment is a package including a package substrate and a package component bonded to the package substrate, the package component including an interposer, an optical die bonded to the interposer, the optical die including an optical coupler, an integrated circuit die bonded to the interposer adjacent the optical die, a lens adapter adhered to the optical die with a first optical glue, a mirror adhered to the lens adapter with a second optical glue, the mirror being aligned with the optical coupler of the optical die, and an optical fiber on the lens adapter, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical glue, the lens adapter, and the first optical glue to the optical coupler of the optical die.

Integrated circuit package and method of forming same

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Polymer layers embedded with metal pads for heat dissipation

A method includes forming a redistribution structure on a carrier substrate, coupling a first side of a first interconnect structure to a first side of the redistribution structure using first conductive connectors, where the first interconnect structure includes a core substrate, where the first interconnect structure includes second conductive connectors on a second side of the first interconnect structure opposite the first side of the first interconnect structure, coupling a first semiconductor device to the second side of the first interconnect structure using the second conductive connectors, removing the carrier substrate, and coupling a second semiconductor device to a second side of the redistribution structure using third conductive connectors, where the second side of the redistribution structure is opposite the first side of the redistribution structure.

Semiconductor device package and methods of manufacture

A die stacking structure, a semiconductor package and a method for forming the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; and a stack of dielectric layers, extending in between the second device dies, and laterally enclosing each of the second device dies. The dielectric layers are respectively formed of a spin-on-glass (SOG) or a polymer, and a lower one of the dielectric layers has a thickness greater than a thickness of another one of the dielectric layers at a higher level.

Die stacking structure, semiconductor package and formation method of the die stacking structure

A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

Fingerprint sensor device and method

Growing community of inventors

Hsin-Chu, Taiwan

Chen-Hua Douglas Yu