Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Solid State Lighting Ltd.

Taiwan Union Technology Corporation

Epistar Corporation

Parabellum Strategic Opportunities Fund LLC

Other

Imec

Chen-Hua Douglas Yu

Chung-Shi Liu

Hao-Yi Tsai

Wen-Chih Chiou

Hsien-Wei Chen

Chuei-Tang Wang

Der-Chyang Yeh

Jing-Cheng Lin

Shin-Puu Jeng

Kuo-Chung Yee

Ming-Fa Chen

Chi-Hsi Wu

Hung-Jui Kuo

Jiun Yi Wu

Mirng-Ji Lii

Shang-Yun Hou

An-Jhih Su

Tin-Hao Kuo

Ming-Da Cheng

Chung-Hao Tsai

Syun-Ming Jang Jang

Wei-Cheng Wu

Hung-Yi Kuo

Sung-Feng Yeh

Chien-Hsun Lee

Chih-Wei Lin

Jui-Pin Hung

Szu-Wei Lu

Yu-Hsiang Hu

Chien Ling Hwang

Cheng-Chieh Hsieh

Shau-Lin Shue

Kai-Chiang Wu

Tsang-Jiuh Wu

Po-Hao Tsai

Ying-Ching Shih

Tien-I Bao

Ching-Hua Hsieh

Wei-Yu Chen

Yu-Feng Chen

Chao-Wen Shih

Tsung-Yuan Yu

Chen-Shien Chen

Chih-Hua Chen

Wei-Hung Lin

Li-Hsien Huang

Meng-Tse Chen

Wei-Ting Chen

Tsung-Ding Wang

Tsung-Shu Lin

Ying-Ju Chen

Hsiu-Jen Lin

Tzuan-Horng Liu

Jie Chen

Han-Ping Pu

Hai-Ching Chen

Yen-Liang Lin

Ming-Che Ho

Chih-Wei Wu

Sih-Hao Liao

Cheng-Lin Huang

Chewn-Pu Jou

Ching-Wen Hsiao

Horng-Huei Tseng

Wen-Shiang Liao

Keng-Chu Lin

Yung-Cheng Lu

Wen-Hsiung Lu

Ming-Hsing Tsai

Feng Wei Kuo

Alexander Kalnitsky

Mei-Yun Wang

Yi-Wen Wu

Mong-Song Liang

Chung-Chi Ko

Chen-Cheng Kuo

Yun-Han Lee

Chia-Shiung Tsai

Chao-Cheng Chen

Chenming Hu

Jeng-Horng Chen

Shy-Jay Lin

Burn Jeng Lin

Chun-Hung Lin

Shih-Chang Chen

Yih Wang

Anthony Yen

Shuo-Mao Chen

Chih-Hao Chang

Li-Hui Cheng

Weng Chang

Tze-Liang Lee

Jin-Yuan Lee

Ying-Lang Wang

Hun-Jan Tao

Chao-Hsiung Wang

Ming Chyi Liu

Ming-Chih Yew

Hsueh-Chang Sung

Pei-Ren Jeng

A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.

Method of manufacturing semiconductor devices with system on chip devices

A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.

Semiconductor package and method

A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed layer. The method further includes plating a first conductive material in the first opening on the seed layer, removing the patterned first photo resist, and after removing the patterned first photo resist, forming a patterned second photo resist over the first conductive material. A second opening in the patterned second photo resist exposes a portion of the first conductive material. The method further includes plating a second conductive material in the second opening on the first conductive material, removing the patterned second photo resist, and after removing the patterned second photo resist, depositing a dielectric layer around the first conductive material and the second conductive material.

Dense redistribution layers in semiconductor packages and methods of forming the same

In an embodiment, a package is provided. The package includes a semiconductor device; an encapsulant laterally surrounding the semiconductor device; and a heat dissipation structure disposed over the semiconductor device and the encapsulant, wherein the heat dissipation structure includes a plurality of pillars and a porous layer extending over sidewalls of the plurality of pillars.

Package with improved heat dissipation efficiency and method for forming the same

A semiconductor package structure and a manufacturing method thereof is provided. The semiconductor package includes a first semiconductor die, including a semiconductor substrate and a first interconnect structure disposed on the semiconductor substrate; a second semiconductor die disposed on and electrically connected to the first semiconductor die, including a second semiconductor substrate and a second interconnect structure; a third interconnect structure, where in the second interconnect structure and the third interconnect structure are disposed on opposite sides of the second semiconductor substrate, and wherein the second interconnect structure is between the first interconnect structure and the third interconnect structure.

Semiconductor package and manufacturing method thereof

A method includes placing a package component over a carrier. The package component includes a device die. A core frame is placed over the carrier. The core frame forms a ring encircling the package component. The method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.

Warpage control of packages using embedded core frame

A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.

Bonding with pre-deoxide process and apparatus for performing the same

A device includes a photonic routing structure including a silicon waveguide, photonic devices, and a grating coupler, wherein the silicon waveguide is optically coupled to the photonic devices and to the grating coupler; an interconnect structure on the photonic routing structure, wherein the grating coupler is configured to optically couple to an external optical fiber disposed over the interconnect structure; and computing sites on the interconnect structure, wherein each computing site includes an electronic die bonded to the interconnect structure, wherein each electronic die of the computing sites is electrically connected to a corresponding photonic device of the photonic devices.

Photonic semiconductor device and method of manufacture

A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

Conductive traces in semiconductor devices and methods of forming same

A method of forming a semiconductor device includes attaching a first local interconnect component to a first substrate with a first adhesive, forming a first redistribution structure over a first side of the first local interconnect component, and removing the first local interconnect component and the first redistribution structure from the first substrate and attaching the first redistribution structure to a second substrate. The method further includes removing the first adhesive from the first local interconnect component and forming an interconnect structure over a second side of the first local interconnect component and the first encapsulant, the second side being opposite the first side. A first conductive feature of the interconnect structure is physically and electrically coupled to a second conductive feature of the first local interconnect component.

Semiconductor package and method of forming thereof

A package includes silicon waveguides on a first side of an oxide layer; photonic devices on the first side of the oxide layer, wherein the photonic devices are coupled to the silicon waveguides; redistribution structures over the first side of the oxide layer, wherein the redistribution structures are electrically connected to the photonic devices; a hybrid interconnect structure on a second side of the oxide layer, wherein the hybrid interconnect structure includes a stack of silicon nitride waveguides that are separated by dielectric layers; and through vias extending through the hybrid interconnect structure and the oxide layer, wherein the through vias make physical and electrical connection to the redistribution structures.

Photonic package and method of manufacture

A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.

Semiconductor device

A chip package structure is provided. The chip package structure includes a first redistribution layer having a bonding portion. The bonding portion includes a dielectric layer. The chip package structure includes a chip structure bonded to the bonding portion. A first width of the dielectric layer of the bonding portion is substantially equal to a second width of the chip structure. The chip package structure includes a protective layer over the first redistribution layer and surrounding the chip structure. A portion of the protective layer extends into the first redistribution layer and surrounds the bonding portion.

Chip package structure with redistribution layer having bonding portion

An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least laterally encapsulating the first die and the through via with an encapsulant, and forming a first redistribution structure over the first die, the through via, and the encapsulant. The forming the first redistribution structure including forming a first via on the through via, and forming a first metallization pattern on the first via, at least one sidewall of the first metallization pattern directly overlying the through via.

Package structures and method of forming the same

A package structure includes a first thermal dissipation structure. The first thermal dissipation structure includes a semiconductor substrate, conductive vias, a thermal transmission structure, first capacitors, bonding pads, and bonding vias. The conductive vias are embedded in the semiconductor substrate. The thermal transmission structure is disposed over the semiconductor substrate and the conductive vias. The thermal transmission structure includes a conductive plane. The first capacitors are at least partially embedded in the thermal transmission structure. The bonding pads and the bonding vias are embedded in the thermal transmission structure. The bonding vias electrically connect the conductive vias and the bonding pads. The conductive plane is in physical contact with sidewalls of at least one of the bonding pads.

Structure having thermal dissipation structure therein and manufacturing method thereof

Growing community of inventors

Hsin-Chu, Taiwan

Chen-Hua Douglas Yu