United Microelectronics Corp.

Chen-Hsiao Wang

Kai-Kuang Ho

Kuang-Hui Tang

Tsong-Lin Shen

Sheng-Wei Hung

Hui-Lung Chou

Chin-Tsai Chang

Yi-Feng Hsu

Yu-Yuan Huang

Tsung-Kai Yu

Chiu-Feng Lee

A copper pillar bump (CPB) structure is provided in the present invention, including a substrate, a pad on the substrate, a passivation layer covering the substrate and exposing the pad, and a copper pillar on the passivation layer and the pad and connecting directly with the pad. The copper pillar is provided with an upper part and a lower part, and a top surface of the lower part includes a first top surface and a second top surface. The second top surface is on one side of the first top surface, and the upper part of the copper pillar is on the first top surface of the lower part. A metal bump is on the copper pillar, wherein parts of the metal bump directly contact the second top surface of the lower part.

Copper pillar bump structure and method of manufacturing the same

A QFN package includes a copper lead frame. The copper lead frame includes a die paddle. A die is fixed on the die pad. A coolant passage is disposed within the die paddle. An inlet passage connects to one end of the coolant passage. An outlet passage connects to another end of the coolant passage. A mold compound encapsulates the copper lead frame and the die.

QFN package and fabricating method of the same

A surface acoustic wave (SAW) device including a substrate is provided. Multiple surface acoustic wave elements are disposed on the substrate. A conductive surrounding structure includes: a wall part, disposed on the substrate and surrounding the surface acoustic wave elements; and a lateral layer part, disposed on the wall part. The lateral layer part has an opening above the surface acoustic wave elements. A cap layer covers the lateral layer part and closes the opening.

Surface acoustic wave device fabrication method

A semiconductor device package structure includes a substrate. The substrate has a circuit structure formed in a die region. The die region is defined by a plurality of scribe lines configured on the substrate. A seal ring is disposed in the substrate and located at a periphery region of the die region, and surrounds at least a portion of the circuit structure. A trench ring is disposed in the substrate between the seal ring and the scribe lines. A packaging passivation cap layer covers over the circuit structure and the seal ring, and covers at least the trench ring.

Semiconductor device package structure and method for fabricating the same

A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern.

Semiconductor chip

A semiconductor structure with an under bump metallization (UBM) layer is provided. The semiconductor structure at least includes a substrate, a metal pad disposed on the substrate, an insulating layer covering the substrate and an edge of the metal pad, wherein at least one recess is disposed within the insulating layer and a first UBM layer contacts the metal pad. The recess is adjacent to the metal pad and the recess is in the shape of a ring. The first UBM layer contacts part of the recess.

Growing community of inventors

Hsinchu, Taiwan

Chen-Hsiao Wang