Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen-Hao Chiang

Chung-Yi Yu

Chi-Ming Chen

Po-Chun Liu

Chia-Shiung Tsai

Han-Chin Chiu

Xiaomeng Chen

Eugene I-Chun Chen

Ru-Liang Lee

Min-Chang Ching

Chih-Ming Chen

Yu-Hung Cheng

Alexander Kalnitsky

Yeur-Luen Tu

Cheng-Ta Wu

Shih-Wei Lin

Yi-Chen Chen

Eugene Chen

Chung-Chieh Hsu

Jiun-Lei Jerry Yu

Chih-Wen Hsiung

Ching I Li

Yao-Chung Chang

Chin-Chia Kuo

Lung Yuan Pan

Ming-Chang Ching

The present disclosure relates to an integrated chip. The integrated chip includes a sensor semiconductor layer. The sensor semiconductor layer is doped with a first dopant. A photodetector is along a frontside of the sensor semiconductor layer. A backside semiconductor layer is along a backside of the sensor semiconductor layer, opposite the frontside. The backside semiconductor layer is doped with a second dopant. A diffusion barrier structure is between the sensor semiconductor layer and the backside semiconductor layer. The diffusion barrier structure includes a third dopant different from the first dopant and the second dopant.

Image sensor with diffusion barrier structure

A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.

Thin film transfer using substrate with etch stop layer and diffusion barrier layer

Various embodiments of the present disclosure are directed towards an optoelectronic device. The device includes a substrate, and a germanium photodiode region extending into an upper surface of the substrate. The germanium photodiode region has a curved upper surface that extends past the upper surface of the substrate. A silicon cap overlies the curved upper surface of the germanium photodiode region. There is an absence of oxide between the curved upper surface of the germanium photodiode region and an upper surface of the silicon cap.

In-situ cap for germanium photodetector

In some embodiments, the present disclosure relates to a semiconductor device, including a substrate including a first semiconductor material and a semiconductor layer extending into an upper surface of the substrate and including a second semiconductor material with a different band gap than the first semiconductor material. The semiconductor device also includes a passive cap including a first dielectric material and disposed along the upper surface of the substrate and on opposite sides of the semiconductor layer, and a photodetector in the semiconductor layer. The first dielectric material includes silicon nitride.

Passive cap for germanium-containing layer

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region having a first doping type disposed in a semiconductor substrate. A second doped region having a second doping type different than the first doping type is disposed in the semiconductor substrate and laterally spaced from the first doped region. A waveguide structure is disposed in the semiconductor substrate and laterally between the first doped region and the second doped region. A photodetector is disposed at least partially in the semiconductor substrate and laterally between the first doped region and the second doped region. The waveguide structure is configured to guide one or more photons into the photodetector. The photodetector has an upper surface that continuously arcs between opposite sidewalls of the photodetector. The photodetector has a lower surface that continuously arcs between the opposite sidewalls of the photodetector.

Semiconductor device comprising a photodetector with reduced dark current

In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

Multi-layered polysilicon and oxygen-doped polysilicon design for RF SOI trap-rich poly layer

A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Method of implanting dopants into a group III-nitride structure and device formed

Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain.

High electron mobility transistor (HEMT) having an indium-containing layer and method of manufacturing the same

The present disclosure, in some embodiments, relates to a transistor device. The transistor device includes a layer of GaN over a substrate. A mobility-enhancing layer of AlGaN is over the layer of GaN and has a first molar fraction z in a first range of between approximately 0.25 and approximately 0.4. A resistance-reducing layer of AlGaN is over the mobility-enhancing layer and has a second molar fraction x in a second range of between approximately 0.1 and approximately 0.15. A source has a source contact and an underlying source region. A drain has a drain contact and an underlying drain region. The source and drain regions extend through the resistance-reducing layer of AlGaN and into the mobility-enhancing layer of AlGaN. The source and drain regions have bottoms over a bottom of the mobility-enhancing layer of AlGaN. A gate structure is laterally between the source and drain contacts.

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Jhongli, Taiwan

Chen-Hao Chiang