Taiwan Semiconductor Manufacturing Comp. Ltd.

Chen Cheng Chou

Sheng-Yuan Lin

Ching-Chen Hao

Chuan-Yi Lin

Tzong-Sheng Chang

Jenn Tsao

Cheng-Ta Wu

Chii-Ming M Wu

Tsu Shih

Bor-Zen Tien

Chu-Wei Hu

Chung-Ren Sun

Tzu Kai Lin

Ming-Chu King

Chao-Chi Chin

Shih-Chang Huang

Techniques in fabricating a fin field-effect transistor (FinFET) include providing a substrate having a fin structure and forming an isolation region having a top surface with a first surface profile. A dopant species is implanted using a tilt angle to edge portions of the top surface. The edge portions are then removed using an etch process. In this respect, the isolation region is modified to have a second surface profile based on an etching rate that is greater than an etching rate used at other portions of the top surface. The second surface profile has a step height that is smaller than a step height corresponding to the first surface profile. The tilt implantation and etching process can be performed before a gate structure is formed, after the gate structure is formed but before the fin structure is recessed, or after the fin structure is recessed.

Tilt implantation for STI formation in FinFET structures

A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

On-chip heat spreader

The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.

Seal ring in an integrated circuit die

A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having a first intervening capacitor dielectric; and, wherein the conductive electrode line portions are electrically interconnected between metallization layers by conductive damascene line portions formed in a second capacitor dielectric and disposed underlying the conductive electrode line portions.

Metal-oxide-metal structure with improved capacitive coupling area

Forming seal ring in an integrated circuit die

A sacrificial semiconductor feature for preventing corrosion that can result during chemical-mechanical planarization (CMP) is disclosed. A semiconductor device of the invention is fabricated at least in part by performing CMP. The device includes a desired semiconductor feature and a sacrificial semiconductor feature. The desired semiconductor feature may have an unbalanced geometric pattern that includes a metallic line ending in at least one tip. The at least one tip is susceptible to corrosion resulting from performing CMP. The sacrificial semiconductor feature is preferably located off the metallic line of the desired semiconductor feature. The sacrificial semiconductor feature attracts charge induced during CMP that is otherwise attracted by the at least one tip of the desired semiconductor feature. The presence of the sacrificial semiconductor feature thus substantially prevents corrosion of the desired semiconductor feature, including its tip(s).

Sacrificial feature for corrosion prevention during CMP

The present invention provides a method for forming and etching a resist protect oxide layer, of which provides improved etch selectivity to a shallow trench isolation and an increased pre-metal dip processing window. The process begins by forming a shallow trench isolation on a semiconductor substrate. The semiconductor substrate has a first area and a second area separated by the shallow trench isolation. A gate is formed on the semiconductor substrate in the first area, adjacent to the shallow trench isolation. In a key step, a resist protect oxide layer comprising a thin silicon oxide layer and an overlying thin nitrogen containing layer, is deposited over the semiconductor substrate, the gate, and the shallow trench isolation. The thin nitrogen containing layer can be composed of silicon nitride or silicon oxynitride. Alternatively, if the notrogen containing layer is composed of silicon oxynitride, the oxide layer can be omitted because oxynitride's stress is less than nitrogen, so the oxynitride could use a native oxide layer as the buffer oxide. The resist protect oxide layer is patterned in an RPO etch step; thereby exposing the first area, including the source and drain regions. A key advantage of the invention is that the RPO etch step can be performed in an endpoint mode where the endpoint is detected by the nitrogen content of the etch chamber ambient. Silicide regions can then be formed on the source and drain regions. A second key advantage of the invention is that the nitrogen containing layer of the resist protect oxide layer has a slower etch rate during pre-metal dip than a resist protect oxide layer composed of only oxide.

Method of forming and etching a resist protect oxide layer including end-point etch

A method for fabricating a junction for a field effect transistor which does not cause distortion of the sidewall spacers during subsequent processing thereby reducing junction depletion and source to drain leakage. The process begins by providing a substrate structure having a gate thereon. Sidewall spacers are formed on the sidewalls of the gate. Impurity ions are implanted into the substrate structure adjacent to the gate to form source and drain regions. A resist protect oxide layer is formed over the substrate structure. The resist protect oxide is patterned by forming a mask over the resist protect oxide layer having an opening over the gate and the source and drain regions. The resist protect oxide layer is selectively etched; thereby removing the resist protect oxide over the source and drain regions without distorting the sidewall spacers. A silicide region is formed on the source and drain regions using a salicide process comprising a pre-amorphous implant and one or more rapid thermal anneal steps. The undistorted sidewall spacers reduce the distance that pre-amorphous implant damage extends under the gate during subsequent processing, which reduces the damage induced impurity ion diffusion under the gate. Because there is less impurity ion diffusion under the gate, junction depletion and source to drain leakage are reduced.

Non-distort spacer profile during subsequent processing

A semiconductor fabrication process, allowing integration of MOSFET devices, and capacitor structures, on a single semiconductor chip, has been developed. The process integration features the use of a MOSFET device, fabricated using a self-aligned contact structure, allowing a reduction in the source and drain area needed for contact. Silicon nitride spacers, used on the sides of the polysilicon gate electrode, protect the polysilicon gate structure, during the opening of a self-aligned contact hole.

Process for integrating a MOSFET device, using silicon nitride spacers

A semiconductor fabrication process, allowing integration of MOSFET devices, and capacitor structures, on a single semiconductor chip, has been developed. The process integration features the use of a MOSFET device, fabricated using a self-aligned contact structure, allowing a reduction in the source and drain area needed for contact. Silicon nitride spacers, used on the sides of the polysilicon gate electrode, protect the polysilicon gate structure, during the opening of a self-aligned contact hole. A self-aligned contact opening, to a source and drain region of a MOSFET device, as well as a capacitor contact opening, to a capacitor structure, are formed using wet-dry etching combinations. These etching combinations result in openings exhibiting sloped profiles, allowing for the attainment of reliable metal coverage, even with the use of sputtered metal depositions.

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Shanhua, Taiwan

Chen Cheng Chou