Texas Instruments Corporation

Flex-p Industries Sdn Bhd.

Chee Kiang Yew

Min Yu Chan

Kian Teng Eng

Boon Pew Chan

Pang Hup Ong

Tuck Fook Toh

Siu Waf Low

Pak Hong Yee

Jing Sua Goh

Chew Weng Leong

Masazumi Amagai

Yong Khim Swee

Jeffrey Tuck Fook Toh

Anthony Louis Coyle

Tito Gelsomini

Bok Leng Ser

Ji Cheng Yang

Sian Yong Khoo

Fung Leng Chen

Colin Chun Sing Lum

Kim Hoch Tey

Piau Fong

Jeffrey Tuck Fock Toh

Matthew Keng Siew Chua

A method is disclosed for packaging a small size memory card, including xD Picture card, Memory Stick&#x2122;, Secure Digital&#x2122; (SD) card, SmartMedia&#x2122; (SM) card, Multimedia card (MMC), CompactFlash&#x2122; (CF) card and PC card, by moulding over to encapsulate a populated printed circuit board (PCB) () to form the standard external dimensions and features of the memory card. The method comprises holding the populated PCB () in place in a cavity () of at least one mould piece; and moulding over both sides of the populated printed circuit board () to encapsulate said board. Various embodiments are disclosed, including means for holding the populated PCB () in the moulding cavity () for the encapsulation process, which includes transfer moulding and injection moulding processes, one or more moulding steps, and moulding over one part of one side of said board before the other side, and/or simultaneously moulding over both sides of said board.

Method for packaging small size memory cards

A method for attaching an integrated circuit chip to an organic substrate comprising the steps of providing an integrated circuit chip having an active and a passive surface, said active surface including a protective polymer layer; activating said polymer layer by exposing it to reactive ion etching plasma, thereby increasing the surface roughness and imparting affinity to adhesion; providing an electrically insulating substrate having first and second surfaces; and contacting said second surface of said substrate to said activated polymer layer on said chip, whereby strong adhesion is exerted at the interface between said layer and said substrate, directly attaching said substrate to said chip.

Direct attachment of semiconductor chip to organic substrate

An integrated circuit package ( ) comprising a substrate ( ) having peripheral openings ( ) and first and second surfaces ( ), a plurality of routing strips ( ) being integral with the substrate ( ), a plurality of pads ( ) centrally disposed on the first surface ( ) and electrically connected with at least one of the routing strips ( ), a chip ( ) having bonding pads ( ) adhered to the second surface ( ) of the substrate ( ), wire bonding ( ) electrically connecting at least one bonding pad ( ) to at least one of the routing strips ( ) and potting material ( ) filling the openings ( ) to adhere the chip ( ) to the substrate ( ) and surrounding the wire bonding ( ), is disclosed.

High density internal ball grid array integrated circuit package

Direct attachment semiconductor chip to organic substrate

A high density unit ( ) comprising a first integrated circuit package ( ) comprising a carrier ( ) having first and second sides ( ), a silicon chip ( ) attached by an adhesive layer ( ) and solder bonding ( ) electrically connecting the silicon chip ( ) to the carrier ( ) stackably and electrically connected to a second integrated circuit package ( ), is disclosed.

Method of fabricating thin integrated circuit units

A method and apparatus for producing an integrated circuit package ( ) comprising a substrate ( ) having an opening ( ) and first and second surfaces ( ), a plurality of routing strips ( ) being integral with the substrate ( ) and extending into the opening ( ), a plurality of pads ( ) disposed on the first and second surfaces ( ) are electrically connected with at least one of the routing strips ( ), wire bonding ( ) electrically connecting at least one bonding pad ( ) to at least one of the routing strips ( ) and a silicon chip ( ) attached to the printed circuit board ( ) by an adhesive material ( ) that provide a seal between silicon chip ( ) and printed circuit board ( ) is disclosed.

Method for adhering and sealing a silicon chip in an integrated circuit package

Integrated circuit package

A high density memory module is disclosed comprising a first packaged integrated circuit memory device having therein a first electrically insulating carrier and a first conductive routing pattern integral with said first carrier, and at least a first semiconductor circuit chip; a second packaged integrated circuit memory device electrically connected to said first device, wherein said first and second devices form a module; said second packaged integrated circuit device having therein a second electrically insulating carrier and second conductive routing pattern integral with said second carrier, and at least a second semiconductor circuit chip; and said second conductive routing pattern including means for modifying the architectural organization of said module.

Modifying memory device organization in high density packages

A high density unit (,) comprising a first integrated circuit package (,) comprising a carrier (,) having first and second sides (,), a silicon chip (,) attached by an adhesive layer (,) and solder bonding (,) electrically connecting the silicon chip (,) to the carrier (,) stackably and electrically connected to a second integrated circuit package (,), is disclosed.

Stacked double sided integrated circuit package

A packaged semiconductor device and a method for burn-in and testing are disclosed. The package comprises a carrier having a pattern of contact pads for electrical connection, and also a pattern of testing pads for electrical characterization such that their location, size and composition allows a conversion to contact pads after the device has been electrically characterized following burn-in. Furthermore, an adapter and a method for burn-in and testing are disclosed for use in testing a variety of different semiconductor devices. The adapter comprises a carrier having a pattern of testing pads bordering the carrier outline, and routing strips which are structured such that the carrier is adaptable to the package of the device being tested.

Semiconductor device testing and burn-in methodology

In accordance with the present invention, there is provided an electrically insulating substrate having first and second surfaces, an outline and an opening. A plurality of electrically conductive routing strips is integral with the substrate. A plurality of contact pads is disposed on the first surface, at least one of the pads being electrically connected with at least one of the routing strips. A semiconductor chip is adhered to the second surface of the substrate. The chip has an outline that is substantially the same as the outline of the substrate. The chip has at least one bonding pad. Wire bonding electrically connects the bonding pad to a routing strip. At least one bus bar is integral with the substrate. The bus bar is positioned remote from the substrate opening and is electrically connected to a bonding pad of the chip and to a contact pad disposed on the first surface of the substrate. At least one grounding pad is disposed on the first surface of the substrate, the grounding pad being electrically connected to at least one bus bar. Encapsulating material fills the opening and covers the wire bonding and the bonding pads. Solder balls are disposed on the contact pads positioned on the first surface of the substrate to enable attachment to wiring boards or other devices or applications. The overall profile of the integrated circuit package of the present invention is preferably about 0.78 mm.

Thin chip-size integrated circuit package

A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.

Method for adhering and sealing a silicon chip in an integrated circuit

An integrated circuit package (30) having first and second layers (76, 78), a plurality of routing pads (82) being integral with the first layer (76), a plurality of upper and lower conduits (18, 118), respectively, disposed on the upper and lower surfaces (92, 94) of the first layer (76), at least one of the upper conduits (18) electrically connected to at least one of the lower conduits (118), a plurality of pads (100) disposed on the second layer (78), vias (84) that electrically connect the pads (100) to the lower conduits (118) and a chip (50) adhered to the second layer (78) having bonding pads (120) at least one of which is electrically connected to at least one of the routing pads (82), is disclosed.

Bridging method of interconnects for integrated circuit packages

An integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending to opening (86), a plurality of pads (100) disposed on the first surface (92) and electrically connected with at least one of the routing strips (82), a chip (50) having bonding pads (120) is adhered to the second surface (84) of the substrate (70) and is of substantially the same outline as substrate (70), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and potting material (90) filling the opening (86) is disclosed.

Chip size integrated circuit package

A high density single inline memory module (140) comprising a printed circuit board (132) and at least one integrated circuit module (130) attached to the first side (134) of the printed circuit board (132), wherein the integrated circuit modules (130) each including first and second integrated circuit packages (30) stackably and electrically connected together is disclosed.

Growing community of inventors

Singapore, Singapore

Chee Kiang Yew