Infineon Technologies Ag

Chee Chian Lim

Yoke Chin Goh

Boon Huat Lim

May Ting Hng

Koh Hoo Goh

A method of attaching a die to a substrate is disclosed. A major surface of the die has an array of electrical contacts, and is covered with a tape segment having an array of apertures in register with the contacts. Solder balls are inserted into the apertures. The die is positioned against a substrate with the solder balls in register with the die pads on the surface of the substrate, and a heat treatment process is performed to bond the conductive elements to the corresponding bond pads.

Method of packaging a die

A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip.

Semiconductor device and method of packaging a semiconductor device with a clip

An electronic component includes lead fingers and a die paddle. A tape pad is mounted below the lead fingers and the die paddle. A first semiconductor chip is bonded onto the tape pad by a layer of first adhesive and a second semiconductor chip is bonded onto the die paddle by a layer of second adhesive. Electrical contacts are disposed between the contact areas of the semiconductors chips and the lead fingers. An encapsulating compound covers part of the lead fingers, the tape pad, the semiconductor chips and the electrical contacts.

Multi-chip electronic package with reduced stress

In an embodiment, a die package may be provided. The die package may include at least one first height adjusting structure, the at least one first height adjusting structure may include a first adjusting height relative to a common plane; at least one second height adjusting structure may be positioned adjacent to the at least one first height adjusting structure, the at least one second height adjusting structure may include a second adjusting height relative to the common plane; wherein the second adjusting height may be different from the first adjusting height relative to the common plane; a first die may be positioned on the at least one first height adjusting structure; and a mold housing substantially surrounding the at least one first height adjusting structure, the at least one second height adjusting structure and the first die.

Die package

A QFN integrated circuit is mounted on a leadframe having multiple lead lands and resin material encapsulates the integrated circuit leaving the lead lands exposed. Subsequently a sawing operation divides the lead lands into multiple leads, and the leadframe and resin material are partitioned to form packages. The pitch of the resultant leads is not limited by the pitch of the lead lands of the leadframe, so the leadframe can be of the relatively cheap generic leadframe variety, in which the pitch of the lead lands is higher than the desired pitch of the leads of the completed package. The sawing operation may further include reshaping the diepad area of the leadframe to produce heat sink fins, for improved heat dissipation. The proposed process is suitable both to produce packages including only a single integrated circuit, and also to produce multi-chip modules.

Fabrication of an integrated circuit package

An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An encapsulation compound covers at least part of the leads, at least part of the semiconductor chip(s), and at least part of the cooling element(s).

Electronic component and method for its production

An encapsulated leadless semiconductor package comprises a first semiconductor die and a second semiconductor die which are electrically connected by a bond wire. The lower surface of the first semiconductor die and the lower surface of the second semiconductor die are essentially coplanar with the lower surface of the encapsulation material.

Semiconductor device and method of assembly

An integrated circuit device comprises a first semiconductor chip on a first substrate and a second semiconductor chip on a second substrate. A side surface of the first semiconductor chip is facing a side surface of the second semiconductor chip. At least one electric cable is provided to be connecting the first substrate to the second substrate.

Integrated circuit device and a method of making the integrated circuit device

A method of manufacturing an integrated circuit package includes: assembling a composite wafer including alternating rows or columns of first and second strips on an adhesive tape, the first strips including a plurality of first dies and the second strips including a plurality of second dies, singulating the first dies from the first strips and the second dies from the second strips, forming a bond wire between respective ones of the first dies and respective ones of the second dies, thereby forming a plurality of component, embedding the components in mold compound, thereby forming a panel and separating the components from the panel, thereby forming individual integrated circuit packages.

Growing community of inventors

Alor Gajah Melaka, Malaysia

Chee Chian Lim