Taiwan Semiconductor Manufacturing Comp. Ltd.

Che-Wei Hsu

Chuei-Tang Wang

Chen-Hua Douglas Yu

Chung-Hao Tsai

Tzu-Chun Tang

Chieh-Yen Chen

Kai-Chiang Wu

Chun-Lin Lu

Yen-Ping Wang

Tin-Hao Kuo

Wei Ling Chang

Chun-Wen Lin

A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

Package structure

An integrated fan-out (InFO) package includes a die, an encapsulant, and a horn antenna. The die has an active surface and a rear surface opposite to the active surface. The encapsulant laterally encapsulates the die. The horn antenna is electrically connected to the die. The horn antenna includes a top wall and a bottom wall respectively located on two opposite sides of the die and the encapsulant. A portion of the top wall is located within a span of the active surface of the die. A portion of the bottom wall is located within a span of the rear surface of the die.

Integrated fan-out package

Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.

System, device and methods of manufacture

An electronic apparatus is provided. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.

Electronic apparatus including antennas and directors

An integrated fan-out (InFO) package includes a die, an encapsulant, a redistribution structure, a slot antenna, an insulating layer, a plurality of conductive structures, and an antenna confinement structure. The encapsulant laterally encapsulates the die. The redistribution structure is disposed on the die and the encapsulant. The slot antenna is disposed above the redistribution structure. The insulating layer is sandwiched between the redistribution structure and the slot antenna. The conductive structures and the antenna confinement structure extend from the slot antenna to the redistribution structure.

An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and at least one first through interlayer via. The first redistribution structure includes a dielectric layer, a feed line at least partially disposed on the dielectric layer and a signal enhancement layer covering the feed line, wherein the signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The at least one first TIV is embedded in the insulation encapsulation and the signal enhancement layer.

Integrated fan-out package and manufacturing method thereof

An integrated fan-out (InFO) package includes a plurality of dies, an encapsulant, an insulating layer, a redistribution structure, a plurality of conductive structures, an antenna confinement structure, and a slot antenna. The encapsulant laterally encapsulates the dies. The insulating layer is disposed over the dies and the encapsulant. The redistribution structure is sandwiched between the insulating layer and the dies. The conductive structures and the antenna confinement structure are embedded in the insulating layer. The slot antenna is disposed on the insulating layer.

A package structure includes a plurality of sub-package structures, a second encapsulant, a second RDL structure and a second conductive terminal. The sub-package structure includes a die, first TIVs, a first encapsulant and an antenna element. The die has a first side and a second side. The first TIVs are laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIVs. The antenna element is on the first side of the die, and on the TIVs and the first encapsulant. The second encapsulant encapsulates sidewalls of the sub-package structures. The second RDL structure is electrically connected to the plurality of sub-package structures. The second conductive terminal is electrically connected to the sub-package structures through the second RDL structure.

Package structure and method of manufacturing the same

An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The first redistribution structure has a dielectric layer and a feed line disposed on the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The insulation encapsulation has a protrusion laterally wraps around the feed line. The insulation encapsulation has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The second redistribution structure is disposed on the die and the insulation encapsulation.

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Kaohsiung, Taiwan

Che-Wei Hsu