Phoenix Pioneer Technology Co., Ltd.

Phoenix LLC

Zhen Ding Technology Co., Ltd.

Quanta Computer Incorporated

Che-Wei Hsu

Shih-Ping Hsu

Chih-Kuai Yang

Chin-Ming Liu

Pao-Hung Chou

Chu-Chin Hu

Chao-Tsung Tseng

Hsin-Chieh Lin

Chao-Chung Tseng

Tung-Yao Kuo

Chiao-Lun Tsai

Ching-Chieh Chang

Chih-Wen Liu

Shih-ping Hsu

The invention discloses a semiconductor package antenna structure and its manufacturing method, wherein the semiconductor package antenna structure includes a first substrate, a semiconductor chip, and a second substrate. The first substrate has at least two stacked first redistribution layers, and each of the first redistribution layers has a first dielectric layer, a first patterned metal layer, and/or a first conductive pillar layer. The semiconductor chip is embedded in the first substrate and coupled to the first redistribution layers. The second substrate has a second redistribution layer, a second conductive pillar layer, and an air dielectric layer, wherein the second conductive pillar layer is protruded from the second redistribution layer. The second substrate is connected to the first substrate by a second conductive pillar layer, and the air dielectric layer is located between the second redistribution layer, the second conductive pillar layer, and the first substrate.

Semiconductor package antenna structure and its manufacturing method

A semiconductor packaging substrate is provided, which includes a build-up circuit structure, at least one fiducial marker structure, and an insulating protective layer. The fiducial marker structure includes a fiducial marker and a second insulating layer covering the fiducial marker. The second insulating layer is made of a transparent insulation material, so that the fiducial marker inside the second insulating layer can be seen through a CCD lens or tool maker microscope for alignment so as to easily create a smaller see-through area and the process parameters can be easily controlled. Besides, the disclosure further provides a manufacturing method for the semiconductor packaging substrate.

Semiconductor packaging substrate and manufacturing method thereof

The present invention provides a semiconductor package structure including a first stacked structure and a second stacked structure, which is stacked on the first stacked structure. The first stacked structure includes a first dielectric layer, a first power chip, a first conductive connecting element, a first conductive pillar and a first patterned conductive layer. The second stacked structure includes a second dielectric layer, a second power chip, a second conductive connecting element, a second conductive pillar, a second patterned conductive layer, and a third patterned conductive layer. The first power chip and the second power chip are stacked to provide a smaller volume semiconductor package structure, that the first power chip and the second power chip may be directly electrically connected through the circuit structure and may eliminate the related disadvantages of the lead frame. In addition, a manufacturing method of a semiconductor package structure is also disclosed.

Semiconductor package structure and manufacturing method thereof

An electronic package is provided and includes an electronic element connected to a plurality of inductor circuits embedded in an insulator of a package substrate by fan-out conductive copper pillars, and at least one shielding layer non-electrically connected to the inductor circuits, where the shielding layer includes a plurality of line segments not connected to each other, such that the shielding layer shields the inductor circuits, thereby achieving the electrical requirements of high-current products while improving the inductance value and quality factor.

Electronic package

The present invention provides a semiconductor package structure including a first dielectric layer, an integrated chip, a second power chip, a first patterned conductive layer, a second patterned conductive layer, a first conductive adhesive part, a second conductive adhesive part, a plurality of first conductive connecting elements and a plurality of second conductive connecting elements, and including a build-up circuit structure below, wherein the integrated chip includes a control chip and a first power chip. By means of integrating the control chip and the first power chip into a single chip, volume of semiconductor package structure can be further reduced. In addition, a manufacturing method of a semiconductor package structure is also provided.

Manufacturing method of semiconductor package structure

A surface acoustic wave (SAW) filter package structure includes a dielectric substrate having a dielectric layer, a first patterned conductive layer, a second patterned conductive layer, and a conductive connection layer. The conductive connection layer is electrically connected between the first patterned conductive layer and the second patterned conductive layer, which are disposed at opposite sides of the dielectric layer. The second patterned conductive layer has a finger electrode portion. An active surface of a chip is faced toward the finger electrode portion. A polymer sealing frame is disposed between the chip and the dielectric substrate and surrounds the periphery of the chip to form a chamber together with the chip and the dielectric substrate. The mold sealing layer is disposed on the dielectric substrate and covers the chip and the polymer sealing frame. A manufacturing method of the SAW filter package structure is also disclosed.

Manufacturing method for surface acoustic wave filter package structure

A smart card fingerprint identification module packaging structure includes a first insulating layer, an insulating protective layer, a shielding layer, a second insulating layer, a fingerprint sensing area and bump pads. A first patterned circuit layer is embedded in the first insulating layer, and part of this layer serves as a first sensing circuit. A second patterned circuit layer is disposed on the second surface of the first insulating layer, and part of this layer serves as a second sensing circuit. A patterned metal layer is disposed on the second insulating layer and covers the outer surface of the second insulating layer as a shielding layer. The shielding layer corresponding to the first and the second sensing circuits is hollowed out to serve as a fingerprint sensing area. The longitudinal projections of the first sensing circuit and the second sensing circuit are staggered from each other without overlapping.

Smart card fingerprint recognition module packaging structure and manufacturing method thereof

A semiconductor package structure includes a chip, a conductive pillar, a dielectric layer, a first patterned conductive layer and a second patterned conductive layer. The chip has a first side with at least a first metal electrode pad and a second side with at least a second metal electrode pad. The conductive pillar, which has a first end and a second end, is disposed adjacent to the chip. The axis direction of the conductive pillar is parallel to the height direction of the chip. The dielectric layer covers the chip and the conductive pillar and exposes the first and second metal electrode pads of the chip and the first and second ends of the conductive pillar. The first patterned conductive layer is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the conductive pillar. The second patterned conductive layer is disposed on a first surface of the dielectric layer and electrically connected between the first metal electrode pad and the first end of the conductive pillar.

Semiconductor package structure and method of making the same

Surface acoustic wave filter package structure and method of manufacturing the same

A package structure for a semiconductor device includes a first conductive layer, a second conductive layer, a first die, a second die, a plurality of first blind via pillars and a conductive structure. The first conductive layer has a first surface and a second surface. The first die and the second die respectively have an active surface and a back surface, which are disposed opposite to each other. There is a plurality of metal pads disposed on the active surface. The first die is attached to the first surface of the first conductive layer with its back surface, and the second die is attached to the second surface of the first conductive layer with its back surface. The first and second conductive layers, the first and second dies, the first blind hole pillars and conductive structure are covered by a dielectric material.

Package structure for semiconductor device and manufacturing method thereof

This disclosure provides a package substrate, a flip-chip package circuit, and their fabrication methods. The package substrate includes: a first wiring layer having a first dielectric material layer and a first metal wire protruding from the first dielectric material layer; a conductive pillar layer formed on the first wiring layer and including a molding compound layer, a second dielectric material layer formed on the molding compound layer, and a metal pillar connected to the first metal wire; a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the metal pillar; and a protection layer formed on the second wiring layer.

Package substrate and flip-chip package circuit including the same

A method of fabricating a packaging substrate is provided, which includes: forming on a carrier a conductor layer having a plurality of openings; forming a plurality of conductive bumps on the conductor layer, wherein each of the conductive bumps has a post body disposed in a corresponding one of the openings and a conductive pad disposed on the conductor layer, the post body being integrally formed with the conductive pad and less in width than the conductive pad; forming a plurality of conductive posts on the conductive pads; forming on the carrier a first insulating layer that encapsulates the conductive bumps and the conductive posts; removing the carrier; and removing the entire conductor layer to expose the post bodies from a first surface of the first insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps.

Method of fabricating packaging substrate

An electronic package and a method for fabricating the same are provided. The method includes bonding a portion of an inactive surface of an electronic component to a thermal conductive layer of a heat dissipating element, encapsulating the electronic component and the thermal conductive layer with an encapsulant, and forming a circuit structure on the encapsulant and electrically connecting the circuit structure to the electronic component. Since the heat dissipating element is bonded to the electronic component through the thermal conductive layer, the heat dissipating effect of the electronic package is improved.

Electronic package having heat dissipating element and method for fabricating the same

A computing device for cooling an electronic component is provided. The computing device includes a chassis with a first end and a second end; fan modules located at the first end of the chassis; and a Peripheral Component Interconnect Express (PCIe) baseboard located at a front side of the chassis. The PCIe baseboard is configured to support placement thereof in the chassis in a first position and a second position. The second position of the PCIe baseboard is a 180-degree rotation from the first position. The PCIe baseboard includes GPU slots for installing a plurality of graphic processing units (GPUs), the GPUs including fan modules.

Growing community of inventors

Hsinchu County, Taiwan

Che-Wei Hsu