Taiwan Semiconductor Manufacturing Comp. Ltd.

Che-Jung Chu

Kuo-Chio Liu

Shyh-Wei Cheng

Cheng-Lin Huang

Chien-Chen Li

Ling-Wei Li

Jui-Chun Weng

Hsi-Cheng Hsu

Chih-Yu Wang

Lieh-Chuan Chen

Yu-Jui Wu

Sheng-Yao Yang

Yu-Ting Hsu

Jung-Kuo Tu

Shiuan-Jeng Lin

Wen-Ming Chen

Chien-Chih Chou

Hung-Lin Chen

Chun-Yen Lo

Hung-Chih Tsai

Meng-Fu Shih

Min-Tar Liu

Heng-Chi Huang

Kuo-Lung Li

Cheng-Liang Cho

Fu-Kang Chiao

Ying-Ting Chang

Matt Chou

A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.

Chip package structure with ring-like structure

A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.

A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.

A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.

Bump layout for coplanarity improvement

Chip package structure including ring-like structure and method for forming the same

Package structures and methods for forming the same are provided. A package structure includes a package component including a first bump. The package structure also includes an intermetallic compound (IMC) on the first bump. The package structure further includes an integrated circuit die including a second bump on the IMC. The integrated circuit die and the package component are bonded together through the first bump and the second bump. The IMC extends from the first bump to the second bump to provide good physical and electrical connections between the first bump and the second bump.

Method for forming package structure including intermetallic compound

A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor structure. The semiconductor structure has a central portion and a peripheral portion surrounding the central portion. The method includes forming first conductive bumps and dummy conductive bumps over a surface of the semiconductor structure. The first conductive bumps are over the central portion and electrically connected to the semiconductor structure. The dummy conductive bumps are over the peripheral portion and electrically insulated from the semiconductor structure. The first conductive bumps each have a first thickness and a first width. The dummy conductive bumps each have a second thickness and a second width. The second thickness is less than the first thickness. The second width is greater than the first width.

Method for forming semiconductor device structure with bumps

A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain, and a gate dielectric layer disposed between the substrate and the gate electrode. At least a portion of the gate dielectric layer is extended beyond the gate electrode toward at least one of the source or the drain.

Metal-oxide-semiconductor field-effect transistor with extended gate dielectric layer

A Micro-Electro-Mechanical System (MEMS) device includes a sensing element, and a proof mass over and overlapping at least a portion of the sensing element. The proof mass is configured to be movable toward the sensing element. A protection region is formed between the sensing element and the proof mass. The protection region overlaps a first portion of the sensing element, and does not overlap a second portion of the sensing element, wherein the first and the second portions overlap the proof mass.

Method of manufacturing a motion sensor device

A one-time programmable (OTP) memory cell with floating gate shielding is provided. A pair of transistors is arranged on a semiconductor substrate and electrically coupled in series, where the transistors comprise a floating gate. An interconnect structure overlies the pair of transistors. A shield is arranged in the interconnect structure, directly over the floating gate. The shield is configured to block ions in the interconnect structure from moving to the floating gate. A method for manufacturing an OTP memory cell with floating gate shielding is also provided.

One-time-programming (OTP) memory cell with floating gate shielding

A method for forming an integrated circuit having Micro-electromechanical Systems (MEMS) includes forming at least two recesses into a first layer, forming at least two recesses into a second layer, the at least two recesses of the second layer being complementary to the recesses of the first layer. An intermediate layer is bonded onto the second layer, the intermediate layer includes through-holes corresponding to the recesses of the second layer. The first layer is bonded to the intermediate layer such that cavities are formed, the cavities to act as operating environments for MEMS devices. The two cavities have different pressures.

Method of fabricating MEMS devices having a plurality of cavities

Motion sensor device and methods for forming the same

An integrated circuit device includes a first layer comprising at least two partial cavities, an intermediate layer bonded to the first layer, the intermediate layer formed to support at least two Micro-electromechanical System (MEMS) devices, and a second layer bonded to the intermediate layer, the second layer comprising at least two partial cavities to complete the at least two partial cavities of the first layer through the intermediate layer to form at least two sealed full cavities. The at least two full cavities have different pressures within.

MEMS devices having a plurality of cavities

A high voltage PMOS device having an improved breakdown voltage is achieved. An asymmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate and source and drain regions within the substrate on either side and adjacent to the gate electrode wherein the source region is encompassed by an n-well. A symmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate, source and drain regions within the substrate on either side and adjacent to the gate electrode, and an n-well in the substrate underlying the gate electrode. The n-well in both structures shifts the breakdown point from the silicon surface to the bottom of the source or drain regions.

Growing community of inventors

Hsinchu, Taiwan

Che-Jung Chu