Mediatek Corporation

Che-Hung Kuo

Hsing-Chih Liu

Che-Ya Chou

Nan-Cheng Chen

Wen-Chou Wu

Tzu-Hung Lin

I-Hsuan Peng

Wei-Che Huang

Nai-Wei Liu

Zheng Zeng

Min-Chen Lin

Ying-Chih Chen

Fu-Yi Han

Yi-Jyun Lee

Chia-Hao Hsu

Tai-Yu Chen

Duen-Yi Ho

Ya-Lun Yang

Chiang-Lin Yen

A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor die, and a first capacitor. The substrate has a wiring structure. The redistribution layer is disposed over the substrate. The first semiconductor die is disposed over the redistribution layer. The first capacitor is disposed in the substrate and is electrically coupled to the first semiconductor die. The first capacitor includes a first capacitor substrate, a plurality of first capacitor cells, and a first through via. The first capacitor substrate has a first top surface and a first bottom surface. The first capacitor cells are disposed in the first capacitor substrate. The first through via is disposed in the first capacitor substrate and electrically couples the first capacitor cells to the wiring structure on the first top surface and the first bottom surface.

Semiconductor package structure

An electronic device includes a main printed circuit board (PCB) assembly comprising a bottom PCB and a semiconductor package mounted on an upper surface of the bottom PCB. The semiconductor package includes a substrate and a semiconductor die mounted on a top surface of the substrate. The semiconductor die and the top surface of the substrate are encapsulated by a molding compound. A top PCB is mounted on the semiconductor package through first connecting elements.

Electronic device with stacked printed circuit boards

A semiconductor package structure includes a frontside redistribution layer, a first semiconductor die, a first capacitor, a conductive terminal, and a backside redistribution layer. The first semiconductor die is disposed over the frontside redistribution layer. The first capacitor is disposed over the frontside redistribution layer and electrically coupled to the first semiconductor die. The conductive terminal is disposed below the frontside redistribution layer and electrically coupled to the frontside redistribution layer. The backside redistribution layer is disposed over the first semiconductor die.

A semiconductor package structure having a frontside redistribution layer, a stacking structure disposed over the frontside redistribution layer and having a first semiconductor die and a second semiconductor die over the first semiconductor die. A backside redistribution layer is disposed over the stacking structure, a first intellectual property (IP) core is disposed in the stacking structure and electrically coupled to the frontside redistribution layer through a first routing channel. A second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is different from the first routing channel and electrically insulated from the frontside redistribution layer.

A semiconductor structure includes a semiconductor die having an active surface, a passivation layer covering the active surface of the semiconductor die, and a post-passivation interconnect (PPI) layer disposed over the passivation layer. The PPI layer includes a ball pad having a first diameter. A polymer layer covers a perimeter of the ball pad. An under-bump-metallurgy (UBM) layer is disposed on the ball pad. The UBM layer has a second diameter that is greater than the first diameter of the ball pad. A solder ball is mounted on the UBM layer.

Ball pad design for semiconductor packages

A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.

Semiconductor device

A semiconductor package structure includes a first redistribution layer, a semiconductor die, a thermal spreader, and a molding material. The semiconductor die is disposed over the first redistribution layer. The thermal spreader is disposed over the semiconductor die. The molding material surrounds the semiconductor die and the thermal spreader.

A semiconductor package includes a package substrate; a semiconductor die mounted on a top surface of the package substrate; a plurality of conductive elements disposed on a bottom surface of the package substrate; and a land-side silicon capacitor disposed on the bottom surface of the package substrate and surrounded by the plurality of conductive elements. The land-side silicon capacitor includes at least two silicon capacitor unit dies adjoined to each other with an integral scribe line region.

Land-side silicon capacitor design and semiconductor package using the same

An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias.

Via array design for multi-layer redistribution circuit structure

One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

Semiconductor package having discrete antenna device

A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property (IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer.

A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor die including a first active surface and a first non-active surface. The semiconductor package structure also includes a second semiconductor die including a second active surface and a second non-active surface. The second semiconductor die is stacked on the first semiconductor die. The first non-active surface faces the second non-active surface. The semiconductor package structure further includes a first redistribution layer (RDL) structure. The first active surface faces the first RDL structure. In addition, the semiconductor package structure includes a second RDL structure. The second active surface faces the second RDL structure.

Semiconductor package structure and method for forming the same

A semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.

Semiconductor package assembly with passive device

A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.

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Tainan, Taiwan

Che-Hung Kuo