Chartered Semiconductor Manufacturing Ltd (corporation)

Hewlett-packard Development Company, L.p.

Other

National University of Singapore

Chaw Sing Ho

Chit Hwei Ng

Ning Ge

Adam L Ghozeil

Lap Chan

Soo Jin Chua

Kin Leong Pey

Kong Hean Lee

R Pg Karunasiri

Michael W Cumbie

Alex See

Trudy L Benjamin

Sanford Chu

Kheng Chok Tee

Lup San Leong

Jian Xun Li

John Oliver

Reynaldo V Villavelez

Yong Feng Lu

Kok Wai Chew

Kin-Leong Pey

Raymond Joy

Hou Tee Ng

Kenneth Hickey

Shao Kai

Tjin Tjin Tjoa

Ser Chia Koh

Xin Ping Cao

Sajan Marokkey Raphael

John Elmslie Martin

Shao Fu Sanford Chu

G Karunasiri

Fong Yau Sam Li

Chan Lap

Yuan Ping Lee

In one example, a printhead having an electrically-functional optical target. The printhead includes a substrate. An optical target having an optically-distinguishable shape and formed from at least one polysilicon strip is deposited on the substrate. An electrical connection to at least one of the polysilicon strips connect the strip into a circuit that is deposited on the substrate.

Electrically-functional optical target

In some examples, a fluid ejection device includes a substrate and a memory cell on the substrate, the memory cell including a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The memory cell includes a channel region between a drain region and a source region. The first dielectric layer is over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The floating gate includes a polysilicon layer, a metal layer, and a second dielectric layer between the polysilicon layer and the metal layer, where the second dielectric layer includes an opening through which the polysilicon layer is electrically connected to the metal layer.

Fluid ejection devices comprising memory cells

Ink property sensing on a printhead is described. In an example, a substrate for a printhead includes a cap layer having bores. Chambers are formed beneath the cap layer in fluidic communication with the bores. Fluid ejectors are disposed in at least a portion of the chambers. At least one ion-sensitive field effect transistor (ISFET) is disposed in a respective at least one of the chambers. An electrode is disposed in each of the chambers having an ISFET and capacitively coupled to said ISFET through a dielectric.

Ink property sensing on a printhead

Examples of fluid ejection apparatuses and methods for making fluid ejection apparatuses are described. An example method may include forming a fluid feed slot in a bulk layer of a substrate, forming a plurality of ink feed channels in at least an epitaxial layer of the substrate, each of the ink feed channels fluidically coupled to the fluid feed slot, and forming a plurality of drop generators over the substrate such that the epitaxial layer of the substrate is between the plurality of drop generators and the bulk layer and such that the each of the drop generators is fluidically coupled to the fluid feed slot by at least one of the ink feed channels.

Fluid ejection apparatuses including a substrate with a bulk layer and a epitaxial layer

A device including a drain, a channel, a floating gate, and a control gate. The channel surrounds the drain and has a channel area. The floating gate includes an active floating gate region that has an active floating gate region area. The control gate is coupled to the active floating gate region via a control capacitance, wherein the active floating gate region area is smaller than the channel area.

Device including active floating gate region area that is smaller than channel area

An example provides an apparatus including a plate having a nozzle orifice, a flat portion, and a first surface having a recess forming a corresponding protrusion extending from a second surface, opposite first surface, of the plate. A substrate may be in spaced relation to the flat portion of the plate such that the protrusion extends toward the substrate and such that the flat portion and the substrate define, at least in part, a chamber.

Apparatuses including a plate having a recess and a corresponding protrusion to define a chamber

A structure and method of fabrication of a capacitor and other devices by providing a semiconductor structure and providing a top insulating layer and conductive features over the semiconductor structure; forming a first conductive layer over the top insulating layer; patterning the first conductive layer to form at least a capacitor bottom plate and a first portion of the first conductive layer; forming a capacitor dielectric layer over the top insulating layer and the capacitor bottom plate and the first portion of the first conductive layer; forming a second conductive layer over the capacitor dielectric layer; and patterning the second conductive layer to form at least a top plate over the bottom plate and a first section of the second conductive layer on the capacitor dielectric layer. The embodiment can further comprise conductive features in the top insulating layer that can underlie the bottom plate, the first portion or/and the first section. The first portion and the first section can form resistors, capacitors or other devices.

Structure and process for a capacitor and other devices

An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make <0.13 um MIM capacitors, (b) undulated copper surfaces, when dielectrics are deposited directly upon it, (c) particles generation concerns during etching, when attempting an etch stop on the bottom MIM plate layers, and finally, (d) dishing during CMP occurs when large copper MIM plates are required, with subsequent capacitance matching problems. The integrated method overcomes the above obstacles and simultaneously forms MIM capacitors, metal resistors and metal interconnects using damascene processing. In addition, the method of forming the MIM capacitors, described herein, can also be used to form anti-fuse devices, in field-programmable gate arrays, FPGA.

MIM and metal resistor formation at CU beol using only one extra mask

A method for making concurrently metal-insulator-metal (MIM) capacitors and a metal resistors in a Cu damascene back-end-of-line process is achieved. The method forms a Cu capacitor bottom metal plate using a dual-damascene process. A Si N or SiC is deposited to form a capacitor dielectric layer on the Cu bottom plate. A metal layer having an upper etch-stop layer is deposited and patterned to form concurrently capacitor top plates and metal resistors. The patterning is terminated in the capacitor dielectric layer to prevent Cu particle contamination. An insulating layer is deposited and via holes are etched to the capacitor top plates and the metal resistors using the upper etch-stop layer to prevent overetching and damage. The method provides a MIM capacitor using only one additional photoresist mask while improving process yield.

Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology

In one embodiment, the present invention recites forming a number of first openings in a first substrate. The present embodiment then recites forming a copper region within each first openings during a damascene process, wherein each copper region has a top surface. The present embodiment then disposes a dielectric layer proximate to the top surface of each of the first copper regions during the damascene process. After depositing a second substrate over the dielectric, a number of second openings in a second substrate are made. Next, a number of second copper regions are formed in the second openings, during the damascene process. The dielectric region is thus disposed between the first copper regions and the second copper regions. In so doing, the dielectric region forms a dielectric barrier between the first copper regions and the second copper regions such that a metal-insulator-metal (MIM) capacitor is formed during a damascene process.

Method to fabricate MIM capacitor using damascene process

A method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper dual damascene process is described. A first dual damascene opening and a pair of second dual damascene openings are provided in a first dielectric layer overlying a substrate. The first and second dual damascene openings are filled with a first copper layer wherein the filled first dual damascene opening forms a logic interconnect and the filled pair of second dual damascene openings forms a pair of capacitor electrodes. The first dielectric layer is etched away between the pair of capacitor electrodes leaving a space between the pair of capacitor electrodes. The space between the pair of capacitor electrodes is filled with a high dielectric constant material to complete fabrication of a vertical MIM capacitor in the fabrication of an integrated circuit device. The fabrication of the capacitor can begin at any metal layer. The process of the invention can be extended to form a parallel capacitor, a series capacitor, stacked capacitors, and so on.

Self-integrated vertical MIM capacitor in the dual damascene process

In one method embodiment, the present invention recites forming an opening in a substrate during a damascene process. The present embodiment then recites forming a dielectric region having two curvilinear surfaces opposite one another at least partially within the opening during the damascene process. The surfaces are curvilinear with respect to a horizontal cross-section. The present embodiment then recites forming a first copper region having a curvilinear surface proximate one of the surfaces of the dielectric region during the damascene process. The present embodiment then recites forming a second copper region having a curvilinear surface proximate a second surface of the dielectric region during the damascene process. In so doing, the dielectric region forms a dielectric barrier between the first copper region and the second copper region such that the vertical cylindrical MIM capacitor is formed.

Method to fabricate MIM capacitor with a curvillnear surface using damascene process

Damascene MIM capacitor with a curvilinear surface structure

A method for forming a void-free epitaxial cobalt silicide (CoSi ) layer on an ultra-shallow source/drain junction. A patterned silicon structure is cleaned using HF. A first titanium layer, a cobalt layer, and a second titanium layer are successively formed on the patterned silicon substrate. The patterned silicon substrate is annealed at a temperature of between about 550&deg; C. and 580&deg; C. in a nitrogen ambient at atmospheric pressure; whereby the cobalt migrates downward and reacts with the silicon structure to form a CoSi /CoSi layer, and the first titanium layer migrates upward and the first titanium layer and the second titanium layer react with the nitrigen ambient to form TiN. The TiN and unreacted cobalt are removed. The silicon structure is annealed at a temperature of between about 825&deg; C. and 875&deg; C. to convert the CoSi /CoSi layer to a CoSi layer. The CoSi layer can optionally be implanted with impurity ions which are subsequently diffused to form ultra-shallow junctions.

Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions

A new method for forming a dual-metal gate CMOS transistors is described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A nitride layer is deposited overlying a gate dielectric layer and patterned to form a first dummy gate in each of the active areas. First ions are implanted to form source/drain regions in each of the active areas not covered by the first dummy gates. The first dummy gates are isotropically etched to form second dummy gates thinner than the first dummy gates. Second ions are implanted to form lightly doped source/drain regions in each of the active areas not covered by the second dummy gates. Dielectric spacers are formed on sidewalls of the second dummy gates and the source/drain regions are silicided. A dielectric layer is deposited and planarized to the second dummy gates. Thereafter, the second dummy gates are removed, leaving gate openings in the dielectric layer. A mask is formed over the PMOS active area. A first metal layer is deposited in the gate opening in the NMOS active area and planarized to the mask. The mask is removed. A second metal layer is deposited in the gate opening in the PMOS active area. The first and second metal layers are polished away to the dielectric layer thereby completing formation of dual-metal gate CMOS transistors in the fabrication of an integrated circuit.

Growing community of inventors

Singapore, Singapore

Chaw Sing Ho