Taiwan Semiconductor Manufacturing Comp. Ltd.

Siliconware Precision Industries Co., Ltd.

Charles Tseng

Ta-Yang Lin

Hsiu-Mei Yu

Kuo-Feng Chen

Kuo-Wei Lin

Yu-Ting Lai

Chin-Te Chen

Chung-Pao Wang

Hwei-Mei Yu

Hui-Peng Wang

A method including the step of providing a substrate having a contact pad, and an under bump metallurgy overlying the contact pad, and a photoresist layer overlying the under bump metallurgy, and wherein the photoresist layer has an opening defined therein down to the under bump metallurgy and aligned with the contact pad. Pretreating the substrate with the first wetting solution prior to plating a first seed layer over the under bump metallurgy. Thereafter, plating a first seed layer is plated onto the under bump metallurgy.

Method and apparatus for pretreating a substrate prior to electroplating

A wafer bumping method comprising the following steps of. A wafer having fields is provided. The wafer having at least one wafer identification character formed thereon within one or more of the fields. A dry film resist is formed over the wafer. Portions of the dry film resist are selectively exposed field by field using a mask whereby the mask is shifted over the one or more fields containing the at least one wafer identification character so that the one or more fields containing the at least one wafer identification character is double exposed after the mask shift so that all of the one or more fields containing the at least one wafer identification character is completely exposed. The selectively exposed dry film resist is developed to remove the non-exposed portions of the dry film resist. Solder is plated over the wafer exposed by the removed portions of the dry film resist to form solder bumps within the fields not containing at least one wafer identification character so that the at least one wafer identification character is readable by optical character recognition.

Method to make wafer laser marks visable after bumping process

A wire-bonded semiconductor device with an improved wire-arrangement scheme is proposed, which can help minimize abnormal wire sweep during encapsulation process. Among the bonding wires on the semiconductor device, those located in corners would be mostly susceptible to abnormal wire sweep, particularly a high-loop bonding wire that is located in immediate adjacency to a low-loop bonding wire located in one corner of the wire-bonded semiconductor device. To solve this problem, the low-loop bonding wire that is located in immediate adjacency to the sweep-susceptible high-loop bonding wire is erected substantially to the same loop height as the high-loop bonding wire, so that it can serve as a shield to the sweep-susceptible high-loop bonding wire against the flow of injected resin during encapsulation process, thus preventing abnormal wire sweep. Alternatively, if a pair of low-loop bonding wires are located in immediate adjacency to the sweep-susceptible high-loop bonding wire and are bonded to a common double-wire bond pad, these two low-loop bonding wires are arranged in an intercrossed manner, which can also help reduce the impact of the injected resin on the sweep-susceptible high-loop bonding wire, thus preventing abnormal wire sweep. The prevention of abnormal wire sweep allows the finished semiconductor device to be more assured in quality and reliability.

Wire-bonded semiconductor device with improved wire arrangement scheme for minimizing abnormal wire sweep

Growing community of inventors

Taichung, Taiwan

Charles Tseng