International Business Machines Corporation

Other

Charles Robert Davis

William Francis Landers

Ronald Dean Goldblatt

Thomas P Duffy

Frank Daniel Egitto

David L Questad

David Noel Light

John Steven Kresge

Ajit Kumar Trivedi

Jae M Park

Howard L Heck

Steven L Hanakovic

John T Kolias

Jonathan David Reid

Richard Hsiao

Vincent James McGahay

Stephen L Buchwalter

Gerald Walter Jones

Henry Atkinson Nye, Iii

Thomas P Gall

Eugene R Skarvinko

Richard R Thomas

Dae Young Jung

Douglas Adam Cywar

James R Loomis

Paul Joseph Hart

Edward P McLeskey

David L Hawken

Daniel C Edelstein

Christopher Vincent Jahnes

Sanjay C Mehta

Sandra Guy Malhotra

Konstantinos I Papathomas

Thomas M Shaw

Donald Seton Farquhar

Jeffrey Curtis Hedrick

Phillip John Restle

David W Wang

Matthew S Angyal

Habib Hichri

Leena Paivikki Buchwalter

Brett H Engel

Richard Andre Wachnik

Stephen Joseph Fuerniss

Scott W Crowder

William J Summa

Jia Lee

Ashit A Mehta

John E Heidenreich, Iii

Lloyd G Burrell

Sharon L Nunes

Edward Paul Barth

John C Hay, Jr

Theodore Harold Zabel

Jeffrey Alan Zimmerman

Diana Llera-Hurlburt

Sanjit Kumar Das

Darbha Suryanarayana

Luis M Ferreiro, Deceased

Lee P Springer

Domenico Tortorella

A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN/Ti or TiN/Al cap is used as a protective coating covering exposed surfaces of a wire bond pad. The TiN/Ti or TiN/Al cap is not affected by alkaline chemistries used in forming the Ni/Au metallization, yet it provides a sufficient electrical pathway connecting the bond pads to the Ni/Au pad metallization.

Method of fabricating a wire bond pad with Ni/Au metallization

An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.

Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor

An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%&#x2013;10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.

Low-k interlevel dielectric layer (ILD)

A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The conductive pads, lines and vias are fabricated during the normal BEOL wiring level integration process. The reinforcing structure provides both vertical and horizontal reinforcement and may be fabricated on the periphery of the active device region or within open regions of the device that are susceptible to delamination and cracking.

Unique feature design enabling structural integrity for advanced low k semiconductor chips

Unique feature design enabling structural integrity for advanced low K semiconductor chips

An integrated circuit, comprising: a semiconductor substrate, a plurality of last metal conductors disposed above said substrate, a bottom metallic layer disposed on said last metal conductors, a top metallic layer, and an alpha absorber disposed between said bottom and top metallic layers, said alpha absorber consisting essentially of a high-purity metal which is an alpha-particle absorber. The metal is, for example, of Ta, W, Re, Os or Ir.

Alpha particle shield for integrated circuit

A multi-level, coplanar copper damascene interconnect structure on an integrated circuit chip includes a first planar interconnect layer on an integrated circuit substrate and having plural line conductors separated by a dielectric material having a relatively low dielectric constant and a relatively low elastic modulus. A second planar interconnect layer on the first planar interconnect layer comprises a dielectric film having an elastic modulus higher than in the first planar interconnect layer and conductive vias therethrough. The vias are selectively in contact with the line conductors. A third planar interconnect layer on the second planar interconnect layer has plural line conductors separated by the dielectric material and selectively in contact with the vias.

Hybrid dielectric structure for improving the stiffness of back end of the line structures

Reinforcement members are disposed along only the transverse edge regions of selected flexible cables of an integral chip carrier and cable assembly, and along only the respectively aligned end areas of the chip carrier portion of the assembly. The reinforcement members may be disposed along all of the flexible cables and end areas of the assembly, or on only selected cable and end area portions of the assembly. The reinforcement members are formed of a tough tear resistant polymer material, such as a hot melt adhesive or polymer tape or film.

Chip carrier and cable assembly reinforced at edges

The present invention provides a method of ablative photodecomposition and forming metal pattern which attains high resolution, is convenient, and employs non-halogenated solvents. The present invention is directed to a process for forming a metal pattern, preferably circuitization on an organic substrate, preferably on a circuit board or component thereof, which comprises coating the substrate with an ablatively-removable coating comprising a polymer resin preferably an acrylate polymer resin and preferably an ultraviolet absorber. A pattern is formed in the polymer coating corresponding to the desired metal pattern by irradiating at least a portion of the polymer coating with a sufficient amount of ultraviolet radiation to thereby ablatively remove the irradiated portion of the polymer coating. Next the patterned substrate is coated with a conductive metal paste to define the metal pattern, and the conductive metal paste is cured. The remaining polymer coating is removed by solvent stripping with nonhalogenated solvents. The present invention further includes patterning electronic structures comprising multilayer circuitry using the above method. An excimer laser is used to form vias or through holes in the electronic structure while simultaneously patterning the polymer coating. This results in perfect alignment between the pattern formed in the polymer coating and the vias or through holes. High resolution circuitry is thus attainable when the electronic structure is subsequently metallized with a conductive metal paste.

High density template: materials and processes for the application of

A method for producing a panel of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of coating a circuitized core material that has been cut into panels with a dielectric material and copper cover sheets; forming circuits from the cover sheets by etching; applying an adhesive polymer across the dielectric material covering the entire area of the panel; applying a cover sheet; drilling the panel to form through-holes and vias; seeding and plating the through-holes and vias with joining metal; applying photo-resist to the panels exposed with an image of the area of the panel to be joined and developed; and etching the cover sheet and the photo-resist away in the area of the panel to be joined to expose the adhesive polymer.

Method for producing multi-layer circuit board and resulting article of

A multi-layer electronic circuit package including at least one electrically conductive plane, a first organic polymeric dielectric material having a first optical absorbency to an ablating wavelength of laser light, and a second organic polymeric dielectric material having a second optical absorbency to the ablating wavelength of laser light. The first and second optical absorbencies being different from each other. A first layer of one of the organic polymeric materials overlays at least one surface of the at least one electrically conductive plane and a second layer of a different organic polymeric material with a different optical absorbency to the material in the first layer overlays the first layer.

Design of high density structures with laser etch stop

Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the per fluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the per fluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.

Method of fabricating a flex laminate package

A multi-layer electronic circuit package including at least one electrically conductive plane, a first organic polymeric dielectric material having a first optical absorbency to an ablating wavelength of laser light, and a second organic polymeric dielectric material having a second optical absorbency to the ablating wavelength of laser light. The first material dielectric material absorbs wavelengths of light that are not the same as wavelengths of light that are absorbed by the second dielectric material. A first layer of the first or the second organic polymeric materials overlays at least one surface of the at least one electrically conductive plane and a second layer of the other of the first and second organic polymeric materials overlays the first layer.

Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the perfluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the perfluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.

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Fishkill, NY, United States of America

Charles Robert Davis