International Business Machines Corporation

Globalfoundries Inc.

Charles J Montrose

Ping-Chuan Wang

Hariklia Deligianni

Richard Paul Volant

Robert Allen Groves

Thomas J Fleischman

John Greg Massey

Robert Daniel Edwards

Stewart E Rauch, Iii

Scott J McAllister

Joshua M Dragula

Nicholas J Lowitz

A method, and forming an associated system, for testing semiconductor devices. Driver channels are provided, each driver channel connected to a storage device via a bus and connected to a respective semiconductor device. Each driver channel includes: a first voltage driver connected to the respective semiconductor device and having a first input for the respective semiconductor device, a second voltage driver connected to the respective semiconductor device and having a second input for the respective semiconductor device, first and second sets of optical switches in the first and second voltage driver respectively, and a microcontroller. All connections between the respective semiconductor device and both the first and second voltage drivers, in response to all optical switches of the first and second set of optical switches being closed. The semiconductor devices are tested, using the driver channels and the test parameters. The test results are provided to the storage device.

Voltage-driven intelligent characterization bench for semiconductor

A method of determining multi-bit upsets (MBU) during soft error rate (SER) testing of a memory device under test is provided. The method may include receiving an error indication based on a comparison between a generated test data pattern written to an address location on the memory device and a stored version of the generated test data pattern read from the address location on the memory device. The error indication is associated with error information associated with the comparison between the generated test data and the stored version of the generated test data. Based on the received error indication, a count value associated with one of a predetermined number of passes a plurality of generated test data patterns traverse between a first and a second memory address location on the memory device is determined. The MBU is determined based on the address location, the error information, and the count value.

Memory tester design for soft error rate (SER) failure analysis

A system for testing a plurality of transistors on a wafer having a storage device or personal computer connected via a bus to a plurality of drivers. Each of the voltage drivers having a microcontroller adapted to receive test parameters and provide test data from a plurality of voltage drivers. By utilizing a bus structure, the personal computer can look on one bus for flags indicating test data is available from a driver and receive the data. In addition a bus may be used to provide test parameters to the drivers. In this manner, multiple drivers may be run at the same time incorporating multiple tests. When data is available it is transferred to the personal computer, for providing test parameters to a plurality of drivers, and connected via a second bus for receiving test results from the plurality of drivers.

A radiation hardened static memory cell, methods of manufacture and design structures are provided. The method includes forming one or more first gate stacks and second gate stacks on a substrate. The method further includes providing a shallow implant process for the one or more first gate stacks such that diffusion regions of the one or more first gate stacks are non-butted junction regions. The method further includes providing a deep implant process for the one or more second gates stack such that diffusions regions of the one or more second gate stacks are butted junction regions.

Radiation hardened memory cell and design structures

A voltage driver is provided having an input to receive test parameters from a microcontroller. The voltage driver having a first amplifier to provide an input to a first switch, based on the test parameters. The first switch having an output to a first connector such as a probe adapted to be connected to a device under test or DUT. A second switch having an input from a second connector to the device under test, the output of the second switch connected to a ground. A third switch has an input connected to the second switch input, the third switch having an output connected to the first connector to the device under test, wherein the first switch is open, and the second and third switch are closed to set the first connector and the second connector to ground. A buffer is provided such that the microcontroller is sets the test parameters in the first voltage driver, the first voltage driver is adapted to provide test data to the buffer. The device is set such that all of the inputs may be set to ground to minimize the possibility of electrostatic discharge building up on the probes and damaging the DUT.

Voltage driver for a voltage-driven intelligent characterization bench for semiconductor

The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.

Apparatus for accurate and efficient quality and reliability evaluation of micro electromechanical systems

A system and method for testing performance characteristics of a MEMs device includes an activation driver configured to receive and drive a waveform to an activation side of the micro electromechanical device and configured to provide readback of an activation voltage and activation current drawn by activation of the micro electromechanical device. A switch driver configured to provide a load to a switch side of the micro electromechanical device provides readback of a load voltage and a load current drawn by the micro electromechanical device. A contact-closure counter and master control card (MCC) is included to control the activation and switch drivers while a digital volt meter (DVM) is in operable communication with the micro electromechanical device to read back analog readback. An analog multiplexer provides the analog readback to a corresponding activation driver or switch driver. A computer having software provides system control, data acquisition, data storage, and data analysis is in operable communication with the multiplexer, DVM and MCC.

Method and apparatus for testing a micro electromechanical device

An apparatus for applying a stress voltage to a device under test includes a stress voltage source, a constant voltage circuit having an input connected to the stress voltage source and an output connected to a control circuit for removing stress when current exceeds a predetermined level which is connected to the device under test. The constant voltage circuit provides a constant stress voltage to the device under test. A monitoring circuit measures the stress voltage applied to the device under test, and measures leakage current through the device under test. A switch has inputs connected to outputs of the monitoring circuit, with the switch being capable of sending a selected output or outputs of the monitoring circuit to a measurement system.

Stress testing for semiconductor devices

A system for stressing and monitoring an electrical device, such that the imposed stress conditions may be terminated at electronic speeds, thereby preventing destruction of the device under test. The system includes stress channels each paired with a control and monitor circuit, such that the control and monitor circuit may shut down the stress if a limiting stress level is detected by the control and monitor circuit. A microprocessor is used to communicate via a digital control bus with each of the paired stress channels and control and monitor circuits to determine the status of the stress channel; control the stress input; and enable or disable the control and monitor circuits. A computer is used to communicate with the microprocessor through a serial interface.

Electromigration and extrusion monitor and control system

A stress-driver circuit for providing a constant voltage (V ) and a constant current (I&equals;V /R) to a bipolar transistor under test. The circuit includes a power source, an op-amp, a FET, and the bipolar transistor. The power source is connected to the bipolar transistor collector. The op-amp has a positive input biased at input voltage (V ) and a negative input having a feedback loop connected to the bipolar transistor emitter. The op-amp output is connected to the FET gate, the FET drain is connected to the power supply, and the FET source is biased to ground through a first resistor and connected to the base of the bipolar transistor. The second resistor is connected at one end to the bipolar transistor emitter and biased to ground at the other end. An automatic trip circuit may be provided to cut off power to the bipolar transistor if the current at the bipolar transistor collector exceeds a predetermined value. One or more parameter readback circuits may be provided in predetermined areas of the stress-driver circuit, each readback circuit providing a readout of current, voltage, or both.

Circuit for bipolar transistor stress and qualification

An apparatus for monitoring and recording multiple gate dielectric leakage currents during a reliability characterization test. The large number of devices tested allows for longer testing at lower voltages thereby minimizing the need to rely on mathematical models. Solid-state multiplexers (MUX) at multiple levels of test apparatus assembly eliminate excess wiring and allow for constant scan monitoring of the devices under test (DUT) without concern for wearout of electromechanical switches. Data resolution is enhanced with fewer data readings per fixed time period during quiescent periods and multiple readings when the leakage current is changing more rapidly. Thus the resolution of the data is maximized during the critical phase of dielectric breakdown allowing for more precise characterizations of gate dielectrics without the need to increase data storage.

Method and apparatus for characterization of gate dielectrics

A power booster and current measuring circuit provides a quiet, accurate voltage to a load (such as a transistor during parametric testing) with a load current of up to 1 ampere, and can measure that load current to an accuracy of &plusmn;0.1 % over a range of currents extending nine orders of magnitude (e.g., 1 ampere to 10 amperes). The load voltage is supplied by a sense driver, a bypass driver, or both. The bypass driver comprises a high-current operational amplifier with a direct feedback loop (e.g., a voltage follower). The sense driver comprises a high-impedance operational amplifier having a feedback loop comprising a high-current operational amplifier connected as a voltage follower and one of a series of sense resistors having different values. The load current is determined by measuring the voltage drop across the sense resistor in the high-impedance operational amplifier feedback loop using an instrumentation amplifier, and dividing the measured voltage drop by the known resistance of the selected sense resistor. Also disclosed is a method of providing a constant voltage to a load over a range of currents and for accurately measuring the current drawn by the load.

Power booster and current measuring unit

A system and method are provided for calculating the period of a mechanical clock while minimizing the effects of extraneous noise. The method of the invention senses three sounds from the clock and calculates the period of the clock based on those three sounds. The method defines a blanking period between the first and the second sounds and the second and the third sounds. During this blanking period, the method ignores all sound to prevent such sound from being mistaken for sounds from the clock. The method also defines an expected time interval between sounds from the clock. The system senses the beats of a mechanical clock while minimizing noise. The system includes a pick-up device, an amplifier coupled to the pick-up device, and a microcontroller configured to control the gain of the amplifier so that the expected time delay interval becomes approximately equal to the actual time interval, thereby minimizing noise. The system also supports a mode in which the durations of two consecutive half-periods are compared to assess their uniformity.

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Clintondale, NY, United States of America

Charles J Montrose