International Business Machines Corporation

Charles H Windisch, Jr

Douglas Willard Stout

Jeanne P Bickford

Howard Smith Landis

Mark Steven Styduhar

Mark D Aubel

Scott T Wameling

Michael T Ross

Disclosed are integrated circuit design systems and methods, wherein selected functional library elements are placed in a layout to meet product specifications and selected hybrid fill-placeable library elements are placed in that same layout to meet at least one feature density rule. Each hybrid fill-placeable library element comprises fill shapes corresponding to specific features subject to a density rule and a marker shape that provides an instruction to ignore any density rule violations within that element for purposes of design rule checking. Placement of the hybrid fill-placeable library elements is performed to balance out density rule violations in functional library elements elsewhere in the layout, thereby avoiding the need for post-processing of the completed IC design to add fill shapes. Optionally, each hybrid fill-placeable library element comprises different fill shapes at different levels and corresponding to different features so that it can be employed to meet multiple different density rules.

Method and system allowing for semiconductor design rule optimization

Power is gated from global terrain to a voltage island while controlling leakage and managing transient power supply noise. The voltage island includes a field effect transistor (FET) power gate, a first connection to a global voltage source and a second connection to a disable signal source, and an island voltage net for supplying voltage to devices on the island. A power gate control circuit is responsive to the disable signal source for generating a test signal for selectively turning off the FET power gate as the disable signal source goes to a logical '1', and for turning on the FET power gate as said disable source goes to a logical '0'. The FET power gate is responsive to the disable signal source being off for connecting the island voltage net to the global voltage source. A turn on finisher circuit is responsive to the disable signal transitioning to on and to the test signal for holding the power gate solidly on; and a turn off finisher circuit is responsive to the disable signal transitioning to off and to the test signal for holding said power gate solidly off.

System and method for power gating

An integrated circuit comprising a first circuit powered by a first power supply. The first circuit sends a first signal referenced to the voltage of the first power supply to a second circuit powered by a second power supply. The second circuit receives the first signal and converts the first signal to a second signal of the same logical value as the first signal and is referenced to the voltage of the second power supply.

Voltage island communications circuits

Growing community of inventors

Essex Junction, VT, United States of America

Charles H Windisch, Jr