Adeia Semiconductor Bonding Technologies Inc.

International Business Machines Corporation

General Electric Company

Other

Charles Gerard Woychik

Cyprian Emeka Uzoh

Arkalgud R Sitaram

Terrence Caskey

Guilian Gao

Hong Shen

Liang Wang

Michael W Newman

Pezhman Monadgemi

Kishor V Desai

Belgacem Haba

Rajesh Katkar

Michael A Gaynes

Mark Vincent Pierson

Zhuowen Sun

Huailiang Wei

Laura Wills Mirkarimi

Chok J Chia

Qwai Hoong Low

Robert Gideon Wodnicki

Ilyas Mohammed

Hiroaki Sato

John Eric Tkaczyk

Kostas I Papathomas

Raymond Albert Fillion

Rayette Ann Fisher

Fatima Lina Ayatollahi

Giana M Phelan

Matthew M Reiss

Paul Allen Mescher

William Rena LaFontaine, Jr

Bong-Sub Lee

Craig S Mitchell

Wayne John Howell

Kevin Matthew Durocher

Lowell Scott Smith

Jerzy Maria Zalesinski

David V Caletka

William E Bernier

David Martin Mills

Robert H Katyl

Amit Kumar Sarkhel

Ajit Kumar Trivedi

Kevin Taylor Knadle

Harold Kohn

Akash Agrawal

Joseph Maryan Milewski

Alan J Emerick

Vilakkudi G Veeraraghavan

Viswanadham Puligandla

Nelson P Franchak

Tamar A Sholtes

James Wilson Rose

Eric A Johnson

Charles Edward Baumgartner

Miguel Angel Jimarez

David James Alcoe

Ellis Chau

Sanjeev Balwant Sathe

Reynaldo Co

Jonathan David Short

Ron Zhang

Robert Stephen Lewandowski

Ramesh R Kodnani

Se Young Yang

Thurston Bryce Youngs, Jr

Cynthia Susan Milkovich

Krishna Darbha

Sangil Lee

Thomas M Culnane

Jennifer Rebecca Sweterlitsch

Daniel Buckminster

Wael Zohni

Richard J Saia

Daniel Jason Erno

Thomas Bert Gorczyca

Brian David Yanoff

Philip Damberg

Yanfeng Du

Ljubisa Dragoljub Stevanovic

James Robert Wilcox

David Richard Esler

David L Thomas

Kenneth Michael Fallon

Richard Alfred Beaupre

Wei-Cheng Tian

Stacey Joy Kennerly

Bongsub Lee

Scott P McGrath

Eric Tosaya

Frederic Lanteri

Charles F Carey

Jean-Francois Gelly

Andrew Cao

Scott D Cogan

Elizabeth Ann Burke

Shubhra Bansal

Vijay S Darekar

Jeffrey Scott Erlbaum

An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

Integrated interposer solutions for 2D and 3D IC packaging

Dies () with integrated circuits are attached to a wiring substrate (), possibly an interposer, and are protected by a protective substrate () attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

Integrated circuits protected by substrates with cavities, and methods of manufacture

A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.

Embedded graphite heat spreader for 3DIC

In a microelectronic component having conductive vias () passing through a substrate () and protruding above the substrate, one or more conductive features (E.A,E.B, or both) are provided above the substrate that wrap around the conductive vias' protrusions (') to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.

Method and structures for heat dissipating interposers

Interposer circuitry () is formed on a possibly sacrificial substrate () from a porous core (') covered by a conductive coating (&#x2033;) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

Interposers with electrically conductive features having different porosities

A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element.

Method of fabricating low CTE interposer without TSV structure

A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.

Structure and method for integrated circuits packaging with increased density

Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a surface of a carrier in a predetermined pattern. The pockets are filled with a reflowable conductive material. Chip dice are coupled to the interposer carrier by fixing terminals of the dice into the pockets. The carrier may include topside and backside redistribution layers to provide fanout for the chip dice, for coupling the interposer to another carrier, board, etc. having a pitch greater than that of the chip dice.

Hybrid 3D/2.5D interposer

A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.

BVA interposer

An insulating second element is provided and overlies a surface of a first element which consists essentially of a material having a CTE of less than 10 ppm/&#xb0; C. and has a first thickness in a first direction normal to the surface. Openings extend in the first direction through the second element. The first element is abraded to produce a thinned first element having a second thickness less than the first thickness. Conductive elements are formed at a first side of the interposer coincident with or adjacent to a surface of the thinned first element remote from the second element. A conductive structure extends through the openings in the second element, wherein the conductive elements are electrically connected with terminals of the interposer through the conductive structure, and the terminals are disposed at a second side of the interposer opposite from the first side.

Method for fabricating a carrier-less silicon interposer

In a microelectronic component having conductive vias () passing through a substrate () and protruding above the substrate, conductive features (E.A,E.B) are provided above the substrate that wrap around the conductive vias' protrusions (') to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Growing community of inventors

San Jose, CA, United States of America

Charles Gerard Woychik