Hewlett-packard Company

Charles G Sodini

Theodore I Kamins

James Robert Eaton

Laurence G Walker

Each memory cell of an x-y addressable semiconductor memory includes a charge storage element serially connected with an I-O (bit) line through a pair of CCD-type transfer gates. One gate is responsive to x-addressing and the other gate to y-addressing. When an x-y address is selected only the charge storage element of the one selected memory cell communicates with the bit line.

X-Y Addressable memory

A one-transistor memory cell is provided in which the depletion-layer capacitance of an MOS capacitor is increased by locally enhancing the substrate dopant concentration. In preferred embodiments the substrate may also be doped adjacent to the substrate-insulator boundary with ions of appropriate conductivity type to form a diode junction in the substrate. The effective capacitance of the memory cell is therefore the capacitance of the insulator in parallel with the substantially increased depletion-layer or diode junction capacitance.

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San Francisco, CA, United States of America

Charles G Sodini