International Business Machines Corporation

Charles Arthur Whiting

Wilbur David Pricer

Charles J Parrish

Harold G Linde

Edward W Conrad

Thomas Benjamin Faure

Joseph Mundenar

Kurt R Kimmel

Matthew C Nicholls

Craig E Schneider

Keith J Machia

James J Colelli

Steven J Holmes

Wu-Song S Huang

Ning Lu

Richard A Phelps

Peter H Mitchell

Dennis P Hogan

John S Smyth

Stephen E Knight

Denise M Puisto

David A Ziemer

Christopher Edward Walsh

Randall A Leggett

Douglas Earl Benoit

Dennis L Macaluso

The present invention relates to determining the location of a defect source which results in a localized elevation on the surface topography of a substrate such as, for example, a silicon wafer. The wafer is placed on a chuck of a semiconductor process tool such as, for example, a photolithographic tool. The upper surface of the wafer is processed by the photolithographic tool to obtain topography measurements. The topography measurements are analyzed to detect the presence of the localized elevation on the upper surface of the wafer. Once the presence of the localized elevation is detected, calculations are performed using the topography measurements to determine whether the source of the localized elevation results from the chuck.

Method for detection of photolithographic defocus

A predictive method is used to compensate for intermediate batch sensitivities which inevitably occur during resist batch changeover. The compensation is applied to historical dose levels to arrive at a new dose level estimating an optimum dose. When the system discovers that a new batch of resist is loaded to a tool, historical data is used to calculate a reference dose for each tool. A batch factor is continuously calculated and using historical data along with the batch factor, a dose adjustment is made to maintain proper image size.

Method of photolithographic exposure dose control as a function of resist sensitivity

A system and method of monitoring and predicting tool overlay settings comprise generating current lot information, generating historical data, categorizing (binning) the historical data into discrete exposure field size ranges, and predicting current lot tool overlay settings based on the current lot information and historical data. The method monitors the overlay errors during each lot pass through each lithographic process operation. Moreover, the method uses a feedback sorting criteria to monitor the tool overlay settings. Furthermore, the current lot information comprises lithographic field dimensions, wherein the lithographic field optics distortion data is derived from the current lithographic process tool. Additionally, the historical data comprises same-bin lithographic field size dimensions of previous lots, which statistically means the data is derived from the same (or similar) bin of like lots, on the current lithographic process tool.

Feedback method utilizing lithographic exposure field dimensions to predict process tool overlay settings

A method and system embodying the present invention for predicting systematic overlay affects in semiconductor lithography. This method is a feed-forward method, based on correlation of current and prior aligned levels, to predict optimum overlay offsets for a given lot. Instead of using population averaging, which ignores process variability, it acknowledges the variability and uses prior measurements to advantage. The principle, backed by production data, is that &ldquo;systematic&rdquo; overlay errors are just that: Image placement errors which persist through processing and will be predictable through time and processing.

Feed-forward lithographic overlay offset method and system

A method and an arrangement for the processing of wafers on post-exposure bake hotplates along multiple processing paths, each of which may result in different integrated circuit images, and adjust the exposure dose based on the path through the process, so as to render the output and resultant image size of each path identical to each other and close to a target value.

Method and arrangement for controlling image size of integrated circuits on wafers through post-exposure bake hotplate-specific dose feedback

An alignment structure ( ) and method for aligning a first circuit image region ( ) of a microelectronic chip ( ) with a second circuit region ( ) of a wafer ( ). The alignment structure comprises a plurality of passive coupling elements ( ) attached to the chip and arranged in a linear array and further comprises a plurality of electrodes ( ) attached to the wafer and arranged in a linear array. The electrodes are arranged into a set of first driven electrodes ( ), a set of second driven electrodes ( ) and a set of sensing electrodes ( ). The first driven, second driven and sensing electrodes are arranged alternatingly with one another and may each include one or more plates ( ). The first and second driven electrodes are driven, respectively, with sine wave signals 180 degrees out of phase with one another. When each passive coupling element is centered over a corresponding sensing electrode, the signals from all of the sensing electrodes are null, indicating that the first circuit image region is aligned with the second circuit image region in the alignment direction. In an alternative embodiment, individual electrodes are configurable into different size first driven, second driven and sensing electrodes to adjust the alignment resolution of the alignment structure.

Capacitive alignment structure and method for chip stacking

A fluid delivery system that includes a fluid delivery tool having a connector element and a location for holding a fluid container. The fluid container location of the tool has a replaceable template with a first key element portion. The fluid delivery system also includes a fluid container having a connector portion for connecting the fluid container to the connector element of the fluid delivery tool so that the fluid in the fluid container may be delivered to the fluid delivery tool. The fluid container may also have a second key element portion distinct from its connector portion and configured to mate with the first key element portion of the tool template. Alternatively, the fluid container may have a body portion integral with and distinct from its connector portion, and a key element is provided on at least a portion of the fluid container body portion and configured to mate with the first key element portion of the tool template. In this configuration, the key element may be removable from or permanently attached to the body portion of the fluid container. The fluid delivery system ensures that only a fluid container key element capable of mating with the key element portion of the template presently located in the fluid delivery tool may be inserted in the container holding location of the fluid delivery tool.

Fluid container with a keying means to prevent improper fluid loading in a fluid delivery tool and a system including such fluid container and fluid delivery tool

A method for the control of wafer surface temperatures during post exposure bake on hot plates of wafers which carry integrated circuits. Also disclosed is a method of maximizing image size uniformity for integrated circuits through the zonal control of temperatures of hot plates during post exposure bake processes for effectively modulating the wafer surface temperatures. Images within a semiconductor wafer integrated circuit line pattern are repeated to process a wafer through the photolithographic patterning process, including post exposure baking, to measure the image linewidths and compare these with an experimentally derived correlation chart; for instance, PEB temperature vs. linewidth for a given or specified photomasking process. The data is then mapped with regard to image size versus hot plate position, and individual heating zones of the hot plate are adjusted in their temperature for maximum degree of image size uniformity and ultimately attaining optimal device speed and pattern line processing uniformity control.

Method for controlling image size of integrated circuits on wafers supported on hot plates during post exposure baking of the wafers

An alignment mark includes aspects of alignment marks used for two or more photolithography systems. Because the new mark includes the features specified for each system it can be read by the detectors of both systems. Since each photolithography system is substantially insensitive to the presence of the aspect used by the other system precision alignment can be achieved by each system.

Dual use alignment aid

A method and apparatus according to the present invention achieves improved lithographic printing of semiconductor wafers. An optimum tilt for projection optics in a lithography tool relative to a wafer in a direction perpendicular to a scanning direction is characterized for each of a plurality of wafer technologies and levels. The corresponding optimum tilt is retrieved from a database to adjust the lithography tool accordingly, depending upon what technology and level is being processed.

Method and apparatus for adjusting a tilt of a lithography tool

An arrangement and method for controlling individual zones of a hot plate which is employed in a post exposure bake step of wafers in the fabrication of semi-conductor devices incorporating photolithographic processes using chemically amplified resist systems. Provided is an in situ temperature-controllable hot plate which includes temperature-controllable surface zones for supporting a standard single wafer, and having loading means which orient the wafer on the hot plate. The hot plate may be segmented into an array of individually controllable heating zones, while mounted above the hot plate is a thermal detection array, such as an infrared(IR) camera or pyroelectric or pyrometric detector which functions to detect and scrutinize the wafer surface temperature with regard to specific locations dispersed across the hot plate surface. This particular data is mapped into the hot plate zones, and the mapped data transmitted into a servo for zonal hot plate adjustment and temperature control.

Hot plate with in situ surface temperature adjustment

A structure and method for removing and recovering an anodically bonded glass device from a substrate using a metal interlayer interposed between the glass and the substrate is provided. As used in semiconductor mask fabrication, the structure comprises a silicon wafer substrate coated with a membrane on which a metal interlayer is disposed. The metal interlayer and a glass device are anodically bonded together. Recovery of the glass device is accomplished by chemically and mechanically removing the wafer and its membrane from the metal interlayer. The membrane is preferably removed using reactive ion etching to which the metal interlayer is resistant. The metal interlayer is then removed from the glass device using a highly corrosive chemical solution. The recovered glass device may then be reused.

Recovery of an anodically bonded glass device from a substrate by use of

A temperature-sensitive film such as a resist is baked onto a semiconductor substrate such as a mask blank by immersion in a heated liquid. A barrier coating may optionally be applied to the substrate prior to immersion and later removed. The substrate is subsequently cooled by immersing the substrate in a cooling liquid or dissolving the heated liquid from the substrate with a rinsing liquid at a temperature sufficiently lower than that of the heated liquid. Temperature uniformity within .+-.0.2.degree. C. is thereby achieved across the regions of varying thickness in the silicon wafer and membrane. Where a resist has been deposited on the mask blank substrate, heating and cooling by immersion results in improved line size control after exposure and development down to 0.25 .mu.m.

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Milton, VT, United States of America

Charles Arthur Whiting