Taiwan Semiconductor Manufacturing Comp. Ltd.

ChaoChieh Tsai

Shun-Liang Hsu

Shou-Zen Chang

Chin-Hsiung Ho

Cheng Kun Lin

Chia-Shiung Tsai

Mong-Song Liang

Jing-Meng Liu

Chi Ming Yang

Yuan-Chang Huang

Juing-Yi Wu

Yuan-Chen Sun

Shaulin Shue

Jau-Jey Wang

Kuan-Yao Wang

Cheng-Kai Liu

A process for fabricating a narrow channel width, MOSFET device, with a reduced reverse narrow channel effect, (RNCE), has been developed. The reduction of the level of dopant depletion, from the channel region, to the interface of a shallow trench &mdash;channel region, has been achieved via use of a large angle, nitrogen ion implantation procedure, performed to exposed surfaces of a shallow trench shape, prior to insulator fill. A nitrogen rich, silicon layer, at the shallow trench &mdash;channel interface, reduces the level of boron depletion, from the channel region, to the RIE damaged region, near the shallow trench shape.

Method to reduce a reverse narrow channel effect for MOSFET devices

A method of fabricating a CMOS device having (1) an anti-SCE block region below a channel region and (2) a metal gate. The invention uses a masking layer having an opening to define the anti-SCE block implant and also the gate structure. The method comprises forming a masking layer having a first opening defining a channel region over the substrate. In a key step, performing an Anti-SCE block implant to create an anti-SCE region. Next, a forming a gate dielectric layer is formed on the substrate in the first opening. A conductive layer is formed over the substrate in the channel region and over the masking layer. The conductive layer is planarized to form a metal gate metal. The barrier layer is removed. LDD regions are formed. Spacers are formed on the sidewall of the metal gate. Source/Drain regions are implanted adjacent to the metal gate stack.

Process of making CMOS device structure having an anti-SCE block implant

A wafer for testing a manufacturing process for vias has a large number of vias (millions) formed into strings that have an open circuit resistance if the string contains a defective via and have a resistance of a few thousand ohms if the string is good. A multiplexor circuit is formed on the test wafer and scans the via strings and produces a binary output denoting that the addressed string is good or defective. The addresses are generated off the wafer by a compute and a defective string is readily identified.

Semiconductor structure for testing vias interconnecting layers of the structure

A process is described for forming a buried, or pocket, ion implant in a semiconductor device. In particular, said pocket is limited to only the drain side of a field effect transistor. To achieve this the photoresist that is used to protect the source and drain regions during ion implantation is located at different distances from the gate pedestal. The photoresist on the source side is placed closer to the gate pedestal than it is on the drain side. As a result, when ions arrive at the surface at a sufficiently shallow angle to be able to penetrate the semiconductor regions immediately beneath the gate oxide, photoresist at the source side blocks the beam while the photoresist on the drain side is far enough away from the gate not to intercept the beam. Thus, a single asymmetrically located pocket is formed in a single step.

Process for manufacturing a single asymmetric pocket implant

A titanium based SALICIDE process that is free of bridging effects is described. A controlled quantity of nitrogen is delivered to the silicon oxide (or nitride) surface during titanium silicide formation. The amount of nitrogen is sufficient to inhibit outdiffusion of silicon at the dielectric areas, but insufficient to affect the sheet resistance of the silicon areas. This is accomplished by means of a titanium/titanium-rich titanium nitride/titanium sandwich that is formed in a single sputtering operation. An optional cap layer of stoichiometric titanium nitride may also be added.

Ti-rich TiN insertion layer for suppression of bridging during a

A method for forming salicide contacts and polycide conductive lines in integrated circuits is described which employs the ion implantation of both silicon and arsenic into polysilicon structures and into source/drain MOSFET elements is described. The method is effective in reducing gate-to-source/drain bridging in the manufacture of sub-micron CMOS integrated circuits and improving the conductivity of sub-micron wide polycide lines. Silicon is implanted into the polysilicon and into the source/drain surfaces forming a amorphized surface layer. Next a low dose, low energy arsenic implant is administered into the amorphized layer. The low dose shallow arsenic implant in concert with the amorphized layer initiates an equalized formation of titanium silicide over both NMOS and PMOS devices in CMOS integrated circuits without degradation of the PMOS devices. Amorphization by the electrically neutral silicon ions permits the use of a lower dose of arsenic than would be required if arsenic alone were implanted. In addition to amorphization, the implanted silicon prevents the formation of microvoids by providing silicon towards titanium silicide formation. The combined amorphization effect of the silicon and arsenic implants also facilitates a silicide phase transition on sub-micron wide polycide lines thereby improving their conductivity.

Silicon and arsenic double implanted pre-amorphization process for

A method for forming salicide contacts and polycide conductive lines in integrated circuits is described which employs the ion implantation of both germanium and arsenic into polysilicon structures and into source/drain MOSFET elements is described. The method is particularly beneficial in the manufacture of sub-micron CMOS integrated circuits. Germanium is implanted into the polysilicon and into the source/drain surfaces forming a amorphized surface layer. Next a low dose, low energy arsenic implant is administered into the amorphized layer. The low dose shallow arsenic implant in concert with the amorphized layer initiates a balanced formation of titanium suicide over both NMOS and PMOS devices in CMOS integrated circuits without degradation of the PMOS devices with an accompanying reduction of gate-to-source/drain shorts. Amorphization by the electrically neutral germanium ions permits the use of a lower dose of arsenic than would be required if arsenic alone were implanted. The combined amorphization effect of the germanium and arsenic implants also facilitates a suicide phase transition on sub-micron wide polycide lines thereby improving their conductivity.

Germanium and arsenic double implanted pre-amorphization process for

A method of forming a capacitor for use in DRAM or other circuits is described. A first polysilicon node, which will form the first capacitor plate, is formed on a layer of first oxide on an integrated circuit wafer. A layer of titanium silicide is formed on the first polysilicon node by depositing titanium and reacting the titanium with the polysilicon using a first rapid thermal anneal. The titanium silicide is then agglomerated by means of a second rapid thermal anneal thereby forming titanium silicide agglomerates on the surface of the first polysilicon node with exposed first polysilicon between the titanium silicide agglomerates. The exposed first polysilicon is then etched thereby increasing the surface area of the surface of the first polysilicon node and forming a first capacitor plate. A layer of second oxide is then formed on the first capacitor plate. A patterned layer of second polysilicon is then formed on the layer of second oxide forming a second capacitor plate.

High effective area capacitor for high density DRAM circuits using

A field oxide region and method of forming a field oxide region using a LOCOS process and nitride spacers formed on the sidewalls of the field oxide regions. During the LOCOS process recesses are formed in the field oxide which result in poor step coverage during successive process steps. Nitride spacers are formed on the sidewalls of the field oxide covering the recesses. The spacers provide a smooth surface over the field oxide and improved step coverage during subsequent process steps.

LOCOS field oxide and field oxide process using silicon nitride spacers

The present invention provides a method of manufacturing a high nitrogen (N) content oxynitride layer 34A 34B over field oxide regions. The oxynitride layer 34A 34B prevents subsequent etches from forming recesses in the field oxide regions 30 and planarizes the surface. The method begins by forming a field oxide region 30 an isolation area in the substrate 22. A high N content oxynitride protection layer 34A 34B (an etch barrier) is then formed surrounding (over and under) the field oxide layer 30. The high N content oxynitride protection layer 34A 34B is formed by heating (e.g., annealing) the substrate in a gas environment comprising ammonia. The high N content oxynitride layer is preferably formed by rapidly thermally annealing the substrate at temperature between about 825.degree. and 875 .degree. C. in an ammonia containing environment with a partial pressure of between about 0.5 and 1.2 kg/cm.sup.2 . The top high N content oxynitride layer 34A over the central area of the field is preferably removed while the top and bottom high content oxynitride layers 34A 34B remain at the periphery of the field oxide.

Method to reduce field oxide loss from etches

A method for forming a CMOS device, with improved yield, performance and reliability characteristics, has been developed. Yield improvements have been addressed by the use of a dual insulator spacer, used to reduce the risk of salicide bridging, as well as the use of pocket implantation regions, used to reduce punchthrough leakage. An ultra shallow junction extension region has been created in a peripheral channel region, reducing the resistance of this region, thus enhancing the performance of the CMOS device. In addition, ultra lightly doped source and drain regions are used to relax reliability concerns, regarding hot electron injection.

CMOS device structure with reduced risk of salicide bridging and reduced

A method for improving the source/drain resistance in the fabrication of an integrated circuit device is described. Gate electrodes are formed on the surface of a semiconductor substrate. Lightly doped regions are implanted into the semiconductor substrate using the gate electrodes as a mask. First spacers are formed on the sidewalls of the gate electrodes. Second spacers are formed on the sidewalls of the first spacers. Heavily doped source and drain regions are implanted into the semiconductor substrate using the gate electrodes and first and second spacers as a mask. Thereafter, the second spacers are removed. A titanium layer is deposited by chemical vapor deposition over the substrate whereby titanium silicide is formed overlying the gate electrodes and overlying the source and drain regions and whereby elemental titanium is deposited overlying the first spacers wherein the titanium silicide overlying the source and drain regions improves the source/drain resistance. The elemental titanium is removed. The substrate is annealed to transform all of the silicide into C54-phase TiSi.sub.2 and the fabrication of the integrated circuit device is completed.

Method of fabricating MOSFET devices

This invention describes a new method for forming self-aligned silicide for application in MOSFET, and a new structure of MOSFET device featuring elevated source and drain, with the objectives of reducing silicide penetration into the source and drain junctions, of eliminating junction spikes, of obtaining smoother interface between the silicide and the silicon substrate, and of reducing the chance of bridging of the silicides on the gate and on the source and drain. The new structure is made by depositing an amorphous layer of silicon on a silicon substrate already patterned with field oxide, gate oxide, polysilicon gate, and silicon nitride spacer on the gate sidewalls. Novel oxide sidewall spacers are then created by first implanting nitrogen into the horizontal surface of the amorphous silicon layer and subsequently thermally oxidizing the part of the amorphous silicon on the vertical sidewalls that is not exposed to nitrogen implantation. A dopant implantation followed by an annealing at 600.degree. C. in nitrogen converts the deposited silicon layer into elevated source and drains. A refractory metal, such as titanium is then deposited over the substrate and, upon rapid thermal annealing, reacts with the elevated source and drain polysilicon to form silicide without consuming the substrate silicon, and without ill effect on the source/drain junctions in the single crystalline silicon. The chance of silicide bridging is greatly reduced due to the special geometry of the novel sidewall oxide spacers.

MOS device structure and integration method

The present invention provides a method of manufacturing a trench having rounded top corners 28 in a substrate. The rounded top edges allow the formation of a gate oxide with a uniform thickness around the trench thereby reducing parasitic field FET problems. The method begins by forming a pad layer 14 over a semiconductor substrate 10. Next, an insulating layer 18 composed of silicon nitride is formed over the pad layer 14. A first opening 19 is formed in the insulating layer 18 and the pad layer 14 exposing the surface of the substrate. The first opening is defined by sidewalls of the pad layer 14 and of the insulating layer 18. An etch buffer layer 20 composed of polysilicon is formed over the resultant surface. In one etch step, the etch buffer layer 20 is anisotropically etched forming spacers 22 on the sidewalls of the pad layer 14 and of the insulating layer 18. The same etch step continues by etching the spacers 22 and the exposed substrate in the first opening 19 thereby forming a trench 26 in the substrate 10. Because the etch has to etch through the spacers before it reached the substrate, the trench 26 has rounded top edges 28 near the pad layer 14. Lastly, the pad layer 14 and the first insulating layer 18 are removed thereby forming the trench 26 with rounded top edges 28.

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Taichung, Taiwan

ChaoChieh Tsai