Yangtze Memory Technologies Co., Ltd.

Wuhan University

Hubei Hope Pharmaceutical Co., Ltd.

Wuhan Iron and Steel (Group) Corp

Chao Zhang

Haibo Li

Yueping Li

Changhyun Lee

Xiaojiang Guo

Bo Du

Ken Hu

Zheng Wang

Yutian Lin

Jionghui Mao

Yunxiang Wu

Joohyun Jin

Wanzhong Liu

Ruoping Wang

Xiaoyang Guo

Zemin Fang

Yanxia Lin

Shenglin Chen

Mingfang Bie

Xiangxin Wang

Zhonghan Luo

A memory device includes selected word lines coupled to first memory cells, a first group of unselected word lines coupled to second memory cells, a second group of unselected word lines coupled to third memory cells; and a peripheral circuit coupled to the selected word lines, the first group of unselected word lines, and the second group of unselected word lines. The peripheral circuit is configured to apply program voltages on the selected word lines, apply first pass voltages on the first group of unselected word lines; and apply second pass voltages on the second group of unselected word lines. A first maximum value of the first pass voltages is different from a second maximum value of the second pass voltages.

Programming for three-dimensional NAND memory

A method for reading a memory device is provided. The memory device includes a plurality of word lines and a plurality of multi-bit memory cells connected to the plurality of word lines, and each of the multi-bit memory cells is configured such that a stored value of the multi-bit memory cell is read through multi-level preset read voltages. The method includes: defining at least one read offset for each of the multi-level preset read voltages respectively, selecting at least one of the multi-level preset read voltages as at least one sampling voltage, reading a multi-bit memory cell on an adjacent word line of a to-be-read multi-bit memory cell, and setting at least one offset flag, each representing a size of a respective one of at least one read offset, according to a sampling reading value of each of the at least one sampling voltage.

Method for reading memory device and memory device

A memory device is provided. The memory device comprises a first plane and a second plane. The memory device further comprises a control circuit coupled to the first plane and the second plane. The control circuit is configured to: simultaneously initiate programming the first plane and the second plane; and in response to the first plane being successfully programmed, the second plane being unsuccessfully programmed, and a programming pulse count of the second plane being less than a predetermined programming pulse count value, keep programming the second plane and disable the first plane.

Memory device and programming method thereof

In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2levels, where N is an integer greater than 1. The level corresponds to one of 2pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a target memory cell of the memory cells into one of x intermediate levels based on all pages of N pages of the piece of N-bits data to be stored in the target memory cell, where x is an integer smaller than 2. The peripheral circuit is also configured to program, in a second pass after the first pass, the target memory cell into one of the 2levels based on all pages of the N pages of the piece of N-bits data to be stored in the target memory cell.

Memory device and multi-pass program operation thereof

A method for programming a three-dimensional (3D) memory device is provided. The 3D memory device has a plurality of memory strings with memory cells vertically stacked, and each memory cell is addressable through a word line and a bit line. The method for programming the 3D memory device includes the following steps: applying a program voltage on a selected word line; applying a first pass voltage on a first group of unselected word lines; and applying a second pass voltage on a second group of unselected word lines, wherein the second pass voltage is different from the first pass voltage.

A memory device is provided. The memory device includes an array of memory cells arranged in a plurality of rows, a plurality of word lines respectively coupled to the plurality of rows of the memory cells, and a peripheral circuit coupled to the word lines. The peripheral circuit is configured to convert a first value to a second value based on a mapping relationship between a read gray code and a program gray code, perform a program operation to program the second value into a memory cell as a state based on the read gray code, and perform a read operation to read out the state from the memory cell based on the read gray code to be the first value.

Program and read operations using different gray codes and memory device for performing the same

This invention proposes a pedestrian re-identification method based on virtual samples, comprising following steps: s) obtaining virtual persons generated by game engine, and generating the virtual samples with person labels by fusing a background of a target dataset and a pose of real persons through a multi-factor variational generation network; s) rendering the generated virtual samples according to lighting conditions; s) sampling the rendered virtual samples according to person attributes of target dataset; s) constructing a training dataset according to virtual samples obtained by sampling to train a pedestrian re-identification model, and verifying identification effect of the trained model. The present invention uses a virtual image generation framework that integrates translation-rendering-sampling to narrow the distribution between virtual images and real images as much as possible to generate virtual samples, and conduct person re-identification model training, which can be effectively and effectively applied to pedestrian datasets in real scenes.

Pedestrian re-identification method based on virtual samples

In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2levels, where N is an integer greater than 1. The level corresponds to one of 2pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a row of target memory cells, such that each of the row of target memory cells is programmed into one of 2/m intermediate levels based on the piece of N-bits data to be stored in the target memory cell, where m is an integer greater than 1. The peripheral circuit is also configured to program, in a second pass after the first pass, the row of target memory cells, such that each target memory cell is programmed into one of the 2levels based on the piece of N-bits data to be stored in the target memory cell.

A method for programming a memory device including a first plane and a second plane is provided. The method includes simultaneously initiating programming of the first plane and the second plane, and in response to the first plane being successfully programmed and the second plane not being successfully programmed, suspending the programming of the first plane, and keeping the programming of the second plane.

Embodiments of erasing methods for a three-dimensional (3D) memory device are disclosed. The 3D memory device includes multiple decks vertically stacked over a substrate, wherein each deck includes a plurality of memory cells. The erasing method includes checking states of the plurality of memory cells of an erase-inhibit deck and preparing the erase-inhibit deck according to the states of the plurality of memory cells. The erasing method also includes applying an erase voltage at an array common source, applying a hold-release voltage on unselected word lines of the erase-inhibit deck, and applying a low voltage on selected word lines of a target deck.

Erasing method for 3D NAND flash memory

A programming method for a memory device includes simultaneously starting to program a first plane and a second plane; and bypassing the first plane and keeping programming the second plane when the first plane has been programmed successfully and the second plane has not been programmed successfully yet.

Programming in a non-volatile memory device includes applying at least one programming pulse to a non-volatile memory cell during a first programming loop; applying at least one programming pulse to the non-volatile memory cell during a second programming loop succeeding the first programming loop; and providing a bitline bias voltage of the non-volatile memory cell according to a result of comparing a threshold voltage of the non-volatile memory cell in the first programming loop with a low verify level and/or a high verify level of a target data state of the non-volatile memory cell and a result of comparing a threshold voltage of the non-volatile memory cell in the second programming loop with the low verify level and/or the high verify level of the target data state of the non-volatile memory cell.

Non-volatile memory device and method for programming in non-volatile memory device by applying multiple bitline bias voltages

Method for programming in non-volatile memory device by applying multiple bitline bias voltages

The present invention disclosed a super dry fog generator comprising a liquid-storage device, an atomization device, an air-blower and a dry separation device with an opening on the top; wherein said dry separation device is above said liquid-storage device and connected with said liquid-storage device; said atomization device is located at the exterior of said liquid-storage device; the two ends of said atomization device are connected with said air-blower and the interior of said dry separation device, respectively; said atomization device is connected with said liquid-storage device, and the liquid entering into the interior of said atomization device is blown into the interior of said dry separation device by said air-blower. The disinfection liquid entering into the atomization device from the liquid-storage device is atomized into small atomized liquid particles by the atomization device, and then the small atomized liquid particles are driven into the dry separation device by said air-blower. After being dried, the small atomized liquid particles are discharged to a space intended to be disinfected, then the disinfection is carried out. The small atomized liquid particles produced by the super dry fog generator of the present invention, whose size is small and much closer to the bacterial size, can be suspended in air for a long time so as to contact fully with the bacteria in air to achieve the purpose of sterilization, and they are convenient and safe with the less corrosion to the objects in the disinfection space.

Growing community of inventors

Wuhan, China

Chao Zhang