Taiwan Semiconductor Manufacturing Comp. Ltd.

Chao-Yang Yeh

Sandeep Kumar Goel

Yun-Han Lee

Chin-Chou Liu

Hau Tao

Chung-Sheng Yuan

Ming-Tsun Lin

Ching-Fang Chen

Mill-Jer Wang

Hung-Chih Lin

Ashok Mehta

Kai-Yuan Ting

Stanley John

Wei-Cheng Wu

William Wu Shen

Hsien-Hsin Sean Lee

Cheng-Hung Yeh

Chih-Chia Chen

Meng-lin Chung

Chi-Ting Huang

Dun-Nian Yaung

Szu-Ying Chen

Tzu-Hsuan Hsu

Sa-Lly Liu

Ze-Ming Wu

Tom Chen

Li-Fu Ding

A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

Test probing structure

A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.

Semiconductor device

Method of manufacturing a semiconductor device

Semiconductor device and method

Method for manufacturing a semiconductor device

An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.

Interposers of 3-dimensional integrated circuit package systems and methods of designing the same

A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.

System and method for validating stacked dies by comparing connections

One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.

Common template for electronic article

Some methods provide an electronic design file, which includes an integrated circuit (IC) component that is operably coupled to a package component. The IC component and package component collectively form a resistor inductor capacitor (RLC) resonant circuit. The method also provides a damping component in the electronic design file. This damping component is configured to reduce a pre-resonant time during which energy exchanged in the RLC resonant circuit approaches a steady-state, and thereby speeds simulation time.

Techniques for fast resonance convergence

An embodiment device package includes a discrete device, a first connector on a bottom surface of the discrete device, and a second connector on a top surface of the discrete device. The first connector bonds the discrete device to a first package component, and the second connector bonds the discrete device to a second package component.

Packages having integrated devices and methods of forming same

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first hybrid bonded device including a first device and a second device hybrid bonded face-to-face to the first device. The first device includes a first substrate having first bonding connectors and a first bonding layer disposed on a surface thereof. A second hybrid bonded device is bonded back-to-back to the first hybrid bonded device. The second hybrid bonded device includes a third device and a fourth device hybrid bonded face-to-face to the third device. The third device includes a second substrate having second bonding connectors and a second bonding layer disposed on a surface. The second bonding connectors of the third device are coupled to the first bonding connectors of the first device, and the second bonding layer of the third device is coupled to the first bonding layer of the first device.

Semiconductor devices and methods of manufacture thereof

Growing community of inventors

Luzhou, Taiwan

Chao-Yang Yeh