Taiwan Semiconductor Manufacturing Comp. Ltd.

Chao-Lung Chen

Cheng-Ming Wu

Po-Han Wang

Ing-Ju Lee

Po-Hsun Huang

Kei-Wei Chen

Ying-Lang Wang

Yu-Ku Lin

Shih-Ho Lin

Szu-Hung Yang

Po-Jen Shih

Che-Min Lin

Hung-San Lu

Chao Yuan Chang

Wen-Chun Hou

Ping-Ching Jiang

Chun-An Kung

Chin-Hsin Hsiao

Ching-Hwanq Su

Shih-Tzung Chang

Shang-Chin Sung

Chung-Chang Chen

A plating apparatus for electroplating a wafer includes a housing defining a plating chamber for housing a plating solution. A voltage source of the apparatus has a first terminal having a first polarity and a second terminal having a second polarity different than the first polarity. The first terminal is electrically coupled to the wafer. An anode is within the plating chamber, and the second terminal is electrically coupled to the anode. A membrane support is within the plating chamber and over the anode. The membrane support defines apertures, wherein in a first zone of the membrane support a first aperture-area to surface-area ratio is a first ratio, and in a second zone of the membrane support a second aperture-area to surface-area ratio is a second ratio, different than the first ratio.

Plating apparatus and method for electroplating wafer

Semiconductor devices are provided. The semiconductor device includes a substrate, an interconnect structure, and a conductive pad structure. The interconnect structure is over the substrate and includes a top metal layer. The conductive pad structure is over the interconnect structure and includes a lower barrier film, an upper barrier film, and an aluminum-containing layer. The lower barrier film is on the top metal layer. The upper barrier film is on the lower barrier film and has an amorphous structure. The aluminum-containing layer is on the upper barrier film. The lower barrier film and the upper barrier film are made of a same material, and a nitrogen atomic percentage of the upper barrier film is higher than a nitrogen atomic percentage of the lower barrier film.

Semiconductor devices having conductive pad structures with multi-barrier films

Methods of fabricating semiconductor devices are provided. The method includes forming an interconnect structure over a substrate. The method also includes forming a passivation layer over the interconnect structure. The method further includes forming an opening in the passivation layer to expose a portion of the interconnect structure. In addition, the method includes sequentially forming a lower barrier film, an upper barrier film, and an aluminum-containing layer in the opening. The lower barrier film and the upper barrier film are made of metal nitride, and the upper barrier film has a nitrogen atomic percentage that is higher than a nitrogen atomic percentage of the lower barrier film and has an amorphous structure.

Methods of fabricating semiconductor devices having conductive pad structures with multi-barrier films

Methods of fabricating semiconductor devices are provided. The method includes providing a substrate and forming an interconnect structure on the substrate. The interconnect structure includes a top metal layer. The method also includes forming a first barrier film on the top metal layer using a first deposition process with a first level of power, and forming a second barrier film on the first barrier film using a second deposition process with a second level of power that is lower than the first level of power. The method further includes forming an aluminum-containing layer on the second barrier film. In addition, the method includes patterning the first barrier film, the second barrier film and the aluminum-containing layer to form a conductive pad structure.

A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.

Copper plating of semiconductor devices using single intermediate low power immersion step

An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and the electrolyte solution in combination with electrolysis. The method is effective in removing particles from via openings of all sizes, including via openings having a width smaller than about 0.2 &#x3bc;m.

Electropolishing method for removing particles from wafer surface

Growing community of inventors

Tainan, Taiwan

Chao-Lung Chen