International Business Machines Corporation

Renesas Electronics Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Samsung Electronics Co., Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Chao-Kun Hu

Andrew Herbert Simon

Chih-Chao Yang

Cyprian Emeka Uzoh

Lynne Marie Gignac

Lawrence Alfred Clevenger

Daniel C Edelstein

Griselda Bonilla

Stephen Mark Rossnagel

Sandra Guy Malhotra

Ronald G Filippi

Thomas M Shaw

Panayotis Constantinou Andricacos

Stephan Grunow

Paul Stephen McLaughlin

Judith Marie Rubino

Michael Rizzolo

Takeshi Nogami

Benjamin David Briggs

Christian Lavoie

Hariklia Deligianni

Kenneth Parker Rodbell

Stephen Edward Greco

Carlos Juan Sambucetti

Deepika Priyadarshini

Kaushik Chanda

Robert Rosenberg

Dale J Pearson

James McKell Edwin Harper

Anthony K Stamper

Jeffrey P Gambino

Theodorus E Standaert

Cyril Cabral, Jr

Timothy Joseph Dalton

Baozhen Li

Katherine Lynn Saenger

Elbert Emin Huang

Koichi Motoyama

Chandrasekhar Narayan

David Lee Rath

Scott Kevin Reynolds

Naftali Eliahu Lustig

Shyng-Tsong Chen

Mahadevaiyer Krishnan

Kaushik Arun Kumar

Michael F Lofaro

Roy Arthur Carruthers

James M Harper

Wei-Tsu Tseng

Wilma Jean Horkans

Sujatha Sankaran

Fen Fen Jamin

Kenneth M Davis

King-Ning Tu

John Owen Dukovic

Chengyu Charles Niu

Tibor Bolom

Steffen K Kaldor

Kwong-Hon Wong

Sean P E Smith

Jeffrey Louis Hurd

Surbhi Mittal

Yun Yu Wang

Ping-Chuan Wang

Soon-Cheon Seo

Oscar Van Der Straten

Kim Yang Lee

William Joseph Gallagher

Roger Allan Quon

Fenton Read McFeely

Mark B Ketchen

Yiheng Xu

Eric Gerhard Liniger

Mark A Jaso

Ismail C Noyan

Roy Charles Iggulden

John Bruley

Xiaomeng Chen

Rainer Florian Schnabel

Frieder Heinrich Baumann

Stefan Weber

Alan W Kleinsasser

Kaushik Chandra

Harikilia Deligianni

Tien Cheng

Zhiguo Sun

Wei-tsui Tseng

Hyeok-sang Oh

Birenda Nath Agarwala

Frieder Hainrich Baumann

An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.

Electrode with alloy interface

Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.

Techniques to improve reliability in Cu interconnects using Cu intermetallics

Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.

Low-temperature diffusion doping of copper interconnects independent of seed layer composition

An electromigration test structure is provided for evaluation of interconnect liner integrity in a semiconductor interconnect structure. The electromigration test structure includes a feeding line; a stress line overlying the feeding line; a first via interconnecting the feeding line and the stress line, wherein the first via comprises a bottom barrier; a first cathode sense and a second cathode sense interconnected to the feeding line; and a first anode sense and a second anode sense interconnected to the feeding line.

Electromigration test structure for Cu barrier integrity and blech effect evaluations

A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.

Copper interconnect with CVD liner and metallic cap

A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.

Discontinuous/non-uniform metal cap structure and process for interconnect integration

An interconnect structure including a noble metal-containing cap that is present at least on some portion of an upper surface of at least one conductive material that is embedded within an interconnect dielectric material is provided. In one embodiment, the noble metal-containing cap is discontinuous, e.g., exists as nuclei or islands on the surface of the at least one conductive material. In another embodiment, the noble metal-containing cap has a non-uniform thickness across the surface of the at least one conductive material.

An interconnect structure including a metallic cap that covers 80 to 99% of the entire surface of an underlying conductive metal feature is provided utilizing a metal reflow process. Laterally extending portions of the conductive metal feature are located on vertical edges of the metallic cap, and each of the laterally extending portions of the conductive metal feature has an uppermost surface that is coplanar with an uppermost surface of the metallic cap.

Metallic capped interconnect structure with high electromigration resistance and low resistivity

An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line.

Interconnect structure for integrated circuits having enhanced electromigration resistance

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Somers, NY, United States of America

Chao-Kun Hu