Taiwan Semiconductor Manufacturing Comp. Ltd.

Chao-Hsun Wang

Mei-Yun Wang

Kuo-Yi Chao

Fu-Kai Yang

Chen-Yuan Kao

Hsien-Cheng Wang

Feng-Yu Chang

Shih-Che Lin

Po-Yu Huang

Wang-Jung Hsueh

Shih-Wen Liu

Rueijer Lin

I-Wen Wu

Yu-Feng Yin

Yun Lee

Pang-Chi Wu

Chen-Ming Lee

Jia-Heng Wang

Wei-Jung Lin

Kuo-Ju Chen

Pei-Yu Chou

Pang-Sheng Chang

Chun-Wei Hsu

Sheng-Hsiung Wang

Li-Chieh Wu

Shih-Hsien Huang

Chia-Hsien Yao

Chung-Huai Chang

Jia-En Lee

Ru-Gun Liu

Jyu-Horng Shieh

Sheng-Liang Pan

Yuan-Tien Tu

Shu-Huei Suen

Shao-Jyun Wu

Chia-Yang Hung

Yi-Chun Chang

Shih-Chieh Wu

Jack Kuo-Ping Kuo

Chia-Sheng Chang

Semiconductor structures and methods for manufacturing the same are provided. The method includes a gate structure formed over a substrate, and a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a dielectric layer formed over the S/D structure, and an S/D contact structure formed over the S/D structure. The S/D contact structure is through the dielectric layer. The semiconductor structure includes a gate contact structure formed through the dielectric layer and landing on the gate structure, and the gate contact structure is in direct contact with the gate structure. The semiconductor structure includes a bridging contact structure covering the gate contact structure and the S/D contact structure, and the bottommost surface of the bridging contact structure is in direct contact with the topmost surface of the S/D contact structure.

Semiconductor structure with conductive_structure

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes nanostructures spaced apart from each other in a first direction and a gate structure formed over and around the nanostructures. The semiconductor structure further includes a gate spacer covering a sidewall of the gate structure and a source/drain structure attached to the nanostructures in a second direction. The semiconductor structure further includes a contact spaced apart from the gate structure by the gate spacer in the second direction and a first conductive structure landing over the gate structure. The semiconductor structure further includes a second conductive structure formed over the gate spacer. In addition, a portion of the second conductive structure is sandwiched between the first conductive structure and the contact.

Semiconductor transistor structure with nanostructures and conductive structure and method for manufacturing the same

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal gate stack over a substrate and an epitaxial structure over the substrate. The semiconductor device structure also includes a conductive contact electrically connected to the epitaxial structure. A topmost surface of the metal gate stack is vertically disposed between a topmost surface of the conductive contact and a bottommost surface of the conductive contact. The semiconductor device structure further includes a first conductive via electrically connected to the metal gate stack. The topmost surface of the conductive contact is vertically disposed between a topmost surface of the first conductive via and a bottommost surface of the first conductive via. In addition, the semiconductor device structure includes a second conductive via electrically connected to the conductive contact.

Structure and formation method of semiconductor device with contact structures

A semiconductor structure includes a metal gate structure having a gate dielectric layer and a gate electrode. A topmost surface of the gate dielectric layer is above a topmost surface of the gate electrode. The semiconductor structure further includes a conductive layer disposed on the gate electrode of the metal gate structure, the conductive layer having a bottom portion disposed laterally between sidewalls of the gate dielectric layer and a top portion disposed above the topmost surface of the gate dielectric layer. The semiconductor structure further includes a contact feature in direct contact with the top portion of the conductive layer.

Forming metal contacts on metal gates

Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Different via configurations for different via interface requirements

An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Dielectric structures for semiconductor device structures

A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Methods of forming air spacers in semiconductor devices

A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.

Interconnect structures and methods of fabrication thereof

A method for forming a FinFET device structure is provided. The method includes forming a gate dielectric layer over a fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer. The method further includes forming a first dielectric layer formed over the gate dielectric layer. In addition, the method includes forming a first conductive layer on the gate dielectric layer. A bottom surface of the first conductive layer is in direct contact a top surface of the gate electrode layer, a sidewall of the first conductive layer is in direct contact the first dielectric layer and spaced apart from the gate dielectric layer.

Method for forming fin field effect transistor (FinFET) device structure with conductive layer between gate and gate contact

Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. Etches are performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.

Via-first process for connecting a contact and a gate electrode

A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure, and a gate spacer layer formed on a sidewall of the gate structure. The FinFET device structure includes a gate contact structure formed over the gate structure, and a first isolation layer surrounding the gate contact structure. A bottom surface of the first isolation layer is lower than a top surface of the gate spacer layer.

Fin field effect transistor (FinFET) device structure with isolation layer and method for forming the same

A method and structure for forming a semiconductor device includes etching back a source/drain contact to define a substrate topography including a trench disposed between adjacent hard mask layers. A contact etch stop layer (CESL) is deposited along sidewall and bottom surfaces of the trench, and over the adjacent hard mask layers, to provide the CESL having a snake-like pattern disposed over the substrate topography. A contact via opening is formed in a dielectric layer disposed over the CESL, where the contact via opening exposes a portion of the CESL within the trench. The portion of the CESL exposed by the contact via opening is etched to form an enlarged contact via opening and expose the etched back source/drain contact. A metal layer is deposited within the enlarged contact via opening to provide a contact via in contact with the exposed etched back source/drain contact.

Contact formation method and related structure

Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity β-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity β-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity β-W phase. The β-W converts to a low-resistivity α-phase of tungsten in the regions not pre-treated with impurities.

Conductive features having varying resistance

A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.

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Chung-Li, Taiwan

Chao-Hsun Wang